View HD4074629R_7782461.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

regarding the change of names mentioned in the document, such as hitachi electric and hitachi xx, to renesas technology corp. the semiconductor operations of mitsubishi electric and hitachi were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although hitachi, hitachi, ltd., hitachi semiconductors, and other hitachi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. renesas technology home page: http://www.renesas.com renesas technology corp. customer support dept. april 1, 2003 to all our customers
cautions keep safety first in your circuit designs! 1. renesas technology corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or an y other rights, belonging to renesas technology corporation or a third party. 2. renesas technology corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained i n these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by renesas technology corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact renesas technology corporation or an authorized renesas technology corporation product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corporation by various means, including the renesas technology corporation semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, an d algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact renesas technology corporation or an authorized renesas technology corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corporation is necessary to reprint or reproduce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a lice nse from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corporation for further details on these materials or the products contained therein.
hd404629r series as microcomputer incorporating a dtmf generator circuit ade-202-048d rev.5.0 sept. 1999 description the hd404629r series is part of the hmcs400-series microcomputers designed to increase program productivity and also incorporate large-capacity memory. each microcomputer has a high precision dual- tone multifrequency (dtmf) generator, lcd controller/driver, a/d converter, input capture circuit, 32- khz oscillator for clock, and four low-power dissipation modes. the hd404629r series includes four chips: the hd404628r with 8-kword rom; the hd4046212r with 12-kword rom; the hd404629r with 16-kword rom; the hd4074629 with 16-kword prom. a program can be written to the prom by a prom writer, which can dramatically shorten system development periods and smooth the process from debugging to mass production. features 1,876-digit 4-bit ram 44 i/o pins, including 10 high-current pins (15 ma, max.) and 20 pins multiplexed with lcd segment pins four timer/counters 8-bit input capture circuit three timer outputs (including two pwm out-puts) two event counter inputs (including one double-edge function) clock-synchronous 8-bit serial interface a/d converter (4 channels 8 bits) lcd controller/driver (52 segments 4 commons) on-chip dtmf generator built-in oscillators ? main clock: 4-mhz ceramic (an external clock is also possible) ? subclock: 32.768-khz crystal eleven interrupt sources ? five by external sources, including three double-edge functions ? six by internal sources subroutine stack up to 16 levels, including interrupts
hd404629r series 2 four low-power dissipation modes ? subactive mode ? standby mode ? watch mode ? stop mode one external input for transition from stop mode to active mode instruction cycle time (min.): 1 m s (f osc = 4 mhz) operation voltage v cc = 2.7 v to 6.0 v (hd404629r) v cc = 2.7 v to 5.5 v (hd4074629) two operating modes ? mcu mode ? mcu/prom mode (hd4074629 only)
hd404629r series 3 ordering information type product name model name rom (words) package mask rom hd404628r hd404628rh 8,192 100-pin plastic qfp (fp-100b) hd404628rfs 100-pin plastic qfp (fp-100a) hd404628rtf 100-pin plastic tqfp (tfp-100b) hd4046212r hd4046212rh 12,288 100-pin plastic qfp (fp-100b) hd4046212rfs 100-pin plastic qfp (fp-100a) hd4046212rtf 100-pin plastic tqfp (tfp-100b) hd404629r hd404629rh 16,384 100-pin plastic qfp (fp-100b) hd404629rfs 100-pin plastic qfp (fp-100a) hd404629rtf 100-pin plastic tqfp (tfp-100b) ztat tm hd4074629 hd4074629h 16,384 100-pin plastic qfp (fp-100b) hd4074629fs 100-pin plastic qfp (fp-100a) hd4074629tf 100-pin plastic tqfp (tfp-100b) ztat tm : zero turn around time ztat is a trademark of hitachi ltd. cautions about operaton! like the ztat tm hd4074629 and the hd404629 series, the hd404629r series has been verified to fully meet the standard electrical characteristics described in the data sheet or other related documents. however, due to differences in the manufacturing process, the type of built-in roms used, and internal wiring patterns, the hd404629r series has different power factors, operating margins, and noise margins. therefore, you should test both of your systems incorporating the ztat tm and mask rom versions. when your system is modified to use an hd404629r series in place of a conventional chip, you should also perform a similar evaluation test to verify performance of your new system.
hd404629r series 4 list of functions product name hd404628r hd4046212r hd404629r hd4074629 rom (words) 8,192 12,288 16,384 16,384 prom ram (digits) 1,876 i/o 44 (max) large-current i/o pins 10 (sink 15 ma max) lcd segment multiplexed pins 20 timer / counter 4 input capture 8 bit 1 timer output 3 (pwm output possible for 2) event input 2 (edge selection possible for 1) serial interface 1 (8-bit syncronous) dtmf generation circuit available a/d converter 8 bit 4 channels lcd controller / driver circuit max. 52 seg 4 com interrupts external 5 (edge selection possible for 3) internal 6 low-power dissipation mode 4 stop mode available watch mode available standby mode available subactive mode available main oscillator ceramic oscillation 400 khz, 800 khz, 2 mhz, 4 mhz crystal oscillation 400 khz, 800 khz, 2 mhz, 4 mhz sub oscillator crystal oscillation 32.768 khz minimum instruction execution time 1 m s (f osc = 4 mhz) operating voltage (v) 2.7 to 6.0 2.7 to 5.5 package 100-pin plastic qfp (fp-100b) 100-pin plastic qfp (fp-100a) 100-pin plastic tqfp (tfp-100b) guaranteed operation temperature (?c) ?0 to +75
hd404629r series 5 pin arrangement fp-100b tfp-100b av an an an an av test osc osc reset x1 x2 gnd d d d d d d d d d d d /stopc d 11 /int 0 cc 1 2 3 ss 1 2 0 1 2 3 4 5 6 7 8 9 10 seg38 seg37 seg36 seg35 seg34 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 r7 /seg20 r7 /seg19 r7 /seg18 r7 /seg17 r6 /seg16 r6 /seg15 r6 /seg14 3 2 1 0 3 2 1 r0 /int r0 /int r0 /int r0 /int r1 /tob r1 /toc r1 /tod r1 /evnb r2 /evnd r2 /sck r2 /si r2 /so r3 /seg1 r3 /seg2 r3 /seg3 r3 /seg4 r4 /seg5 r4 /seg6 r4 /seg7 r4 /seg8 r5 /seg9 r5 /seg10 r5 /seg11 r5 /seg12 r6 /seg13 0 1 2 3 0 1 2 3 0 1 0 1 2 3 0 1 2 3 0 1 2 3 0 vt toner tonec v v v v com4 com3 com2 com1 seg52 seg51 seg50 seg49 seg48 seg47 seg46 seg45 seg44 seg43 seg42 seg41 seg40 seg39 cc 3 2 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 2 3 top view 0 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 99 98 97 96 ref
hd404629r series 6 pin arrangement fp-100a toner vt av an an an an av test osc osc reset x1 x2 gnd d d d d d d d d d d d /stopc d /int r0 /int r0 /int r0 /int seg41 seg40 seg39 seg38 seg37 seg36 seg35 seg34 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 r7 /seg20 r7 /seg19 r7 /seg18 r7 /seg17 r6 /seg16 r6 /seg15 r6 /seg14 r6 /seg13 r5 /seg12 3 2 1 0 3 2 1 0 3 r0 /int r1 /tob r1 /toc r1 /tod r1 /evnb r2 /evnd r2 /sck r2 /si r2 /so r3 /seg1 r3 /seg2 r3 /seg3 r3 /seg4 r4 /seg5 r4 /seg6 r4 /seg7 r4 /seg8 r5 /seg9 r5 /seg10 r5 /seg11 tonec v v v v com4 com3 com2 com1 seg52 seg51 seg50 seg49 seg48 seg47 seg46 seg45 seg44 seg43 seg42 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 0 1 2 3 4 5 6 7 8 9 0 1 2 3 0 1 2 10 43 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 cc 3 2 1 11 ref cc 0 1 2 3 ss 1 2
hd404629r series 7 pin description pin number item symbol fp-100b tfp-100b fp-100a i/o function power v cc 97 99 applies power voltage supply gnd 13 15 connected to ground test test 7 9 i used for factory testing only: connect this pin to v cc reset reset 10 12 i resets the mcu oscillato r osc 1 8 10 i input/output pins for the internal oscillator circuit: osc 2 9 11 o connect them to a ceramic oscillator ,crystal oscillator or connect osc 1 to an external oscillator curcuit x1 11 13 i used for a 32.768-khz crystal for clock purposes. x2 12 14 o if not to be used, fix the x1 pin to v cc and leave the x2 pin open. port d 0 ? 9 14?3 16?5 i/o input/output pins addressed by individual bits; pins d 0 ? 9 are high-current pins that can each supply up to 15 ma d 10 , d 11 24, 25 26, 27 i input pins addressable by individual bits r0 0 ?7 3 26?7 28?9 i/o input/output pins addressable in 4-bit units interrupt int 0 , int 1 , int 2 ?nt 4 25?9 27?1 i input pins for external interrupts stop clear stopc 24 26 i input pin for transition from stop mode to active mode serial sck 35 37 i/o serial interface clock input/output pin interface si 36 38 i serial interface receive data input pin so 37 39 o serial interface transmit data output pin timer tob, toc, tod 30?2 32?4 o timer output pins evnb , evnd 33, 34 35, 36 i event count input pins lcd v 1 , v 2 , v 3 94?6 96?8 power pins for lcd controller/driver; may be left open during operation since they are connected by internal voltage division resistors. voltage conditions are: v cc v 1 v 2 v 3 gnd com1?om4 90?3 92?5 o common signal pins for lcd seg1?eg52 38?9 40?1 o segment signal pins for lcd
hd404629r series 8 pin number item symbol fp-100b tfp-100b fp-100a i/o function a/d converter av cc 1 3 power pin for a/d converter: connect it to the same potential as v cc , as physically close to the v cc pin as possible av ss 6 8 ground for av cc : connect it to the same potential as gnd, as physically close to the gnd pin as possible an 0 ?n 3 2? 4? i analog input pins for a/d converter dtmf toner 99 1 o output pin for dtmf row signals tonec 98 100 o output pin for dtmf column signals vt ref 100 2 reference voltage pin for dtmf signals. voltage conditions are: v cc 3 vt ref 3 gnd
hd404629r series 9 block diagram : high current pins reset test stop c osc 1 osc 2 x1 x2 v cc gnd hmcs400 cpu rom ram timer a 8-bit free-running timer timer b 8-bit free-running / reload timer d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 d 11 r4 0 r4 1 r4 2 r4 3 r0 0 r0 1 r0 2 r0 3 r1 0 r1 1 r1 2 r1 3 r2 0 r2 1 r2 2 r2 3 r3 0 r3 1 r3 2 r3 3 r5 0 r5 1 r5 2 r5 3 toc evnb tob av cc av ss an 0 an 1 an 2 an 3 v 1 v 2 v 3 com1 com2 com3 com4 seg1 seg2 seg3 seg52 a/d converter 4 channels x 8 bits external interrupt control circuit int 0 int 1 int 2 int 3 int 4 r6 port r5 port r4 port r3 port r2 port r1 port r0 port d port r7 port r6 0 r6 1 r6 2 r6 3 r7 0 r7 1 r7 2 r7 3 evnd tod clock-synchronous 8-bit serial interface sck si so lcd controller / driver circuit 52 segments x 4 commons to dtmf generation circuit vt ref toner tonec timer c 8-bit free-running / reload timer timer d 8-bit free-running / reload timer
hd404629r series 10 memory map rom memory map the rom memory map is shown in figure 1 and described below. $000f $0fff $3fff $003f vector address (16 words) zero-page subroutine (64 words) pattern (4,096 words) hd404628r program (8,192 words) $0000 $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000a $000b $000c $000d $000e $000f jmpl instruction (jump to reset, stopc routine) jmpl instruction (jump to int routine) 0 jmpl instruction (jump to timer a routine) jmpl instruction (jump to timer b, int routine) 2 jmpl instruction (jump to timer c, int routine) 3 jmpl instruction (jump to timer d, int routine) 4 jmpl instruction (jump to int routine) 1 jmpl instruction (jump to a/d, serial routine) $1fff $2fff hd4046212r program (12,288 words) hd404629r, hd4074629 program (16,384 words) $0010 $0040 $1000 $2000 $3000 rom address rom address figure 1 rom memory map vector address area ($0000?000f): reserved for jmpl instructions that branch to the start addresses of the reset and interrupt routines. after mcu reset or an interrupt, program execution continues from the vector address. zero-page subroutine area ($0000?003f): reserved for subroutines. the program branches to a subroutine in this area in response to the cal instruction. pattern area ($0000?0fff): contains rom data that can be referenced with the p instruction. program area ($0000?1fff: hd404628r; $0000?2fff: hd4046212r; $0000?3fff; hd404629r, hd4074629): used for program coding.
hd404629r series 11 ram memory map the mcu contains a 1,876-digit 4-bit ram area consisting of a memory register area, an lcd data area, a data area, and a stack area. in addition, an interrupt control bits area, special register area, and register flag area are mapped onto the same ram memory space as a ram-mapped register area outside the above areas. the ram memory map is shown in figure 2 and described below. ram-mapped register area ($000?03f): interrupt control bits area ($000?003) this area is used for interrupt control bits (figure 3). these bits can be accessed only by ram bit manipulation instructions (sem/semd, rem/remd, and tm/tmd). however, note that not all the instructions can be used for each bit. limitations on using the instructions are shown in figure 4. special function register area ($004?01f, $024?03f) this area is used as mode registers and data registers for external interrupts, serial interface, timer/counters, lcd, a/d converter, and as data control registers for i/o ports. the structure is shown in figures 2 and 5. these registers can be classified into three types: write-only (w), read-only (r), and read/write (r/w). the sem, semd, rem, and remd instructions can be used for the lcd control register (lcr: $01b), but ram bit manipulation instructions cannot be used for other registers. register flag area ($020?023) this area is used for the dton, wdon, and other register flags and interrupt control bits (figure 3). these bits can be accessed only by ram bit manipulation instructions (sem/semd, rem/remd, and tm/tmd). however, note that not all the instructions can be used for each bit. limitations on using the instructions are shown in figure 4.
hd404629r series 12 a/d mode register (amr) data (464 digits) v = 1 (bank = 1) $000 $000 $040 $050 $003 $004 $005 $006 $007 $008 $009 $00a $00b $00c $00d $00e $00f $010 $011 $012 $013 $014 $020 $023 $032 $033 $034 $035 $036 $037 $038 $03f $00a $00b $00e $00f w w r/w w w w w w w w w w w w w w w r r r r w r/w r/w r/w r/w r/w r/w $090 $25f $3c0 $260 ram-mapped register area memory registers (10 digits) lcd display area (52 digits) not used data (464 digits 3) v = 0 (bank 0) v = 1 (bank 1) v = 2 (bank 2) data (352 digits) stack (64 digits) interrupt control bits area port mode register a (pmra) serial mode register a (smra) serial data register lower (srl) serial data register upper (sru) timer mode register a (tma) timer mode register b1 (tmb1) timer b (trbl/twbl) (trbu/twbu) miscellaneous register (mis) timer mode register c1 (tmc1) timer c (trcl/twcl) (trcu/twcu) timer mode register b2 (tmb2) timer mode register d2 (tmd2) register flag area port r0 dcr (dcr0) port r1 dcr (dcr1) port r2 dcr (dcr2) port r3 dcr (dcr3) port d 0 ? 3 dcr (dcd0) port d 4 ? 7 dcr (dcd1) port d 8 and d 9 dcr (dcd2) not used v register (v) data (464 digits) v = 0 (bank = 0) the data area has three banks: bank 0 (v = 0) to bank 2 (v = 2). two registers are mapped on the same area. 10 11 14 15 timer read register b lower (trbl) timer read register b upper (trbu) timer read register c lower (trcl) timer read register c upper (trcu) timer write register b lower (twbl) timer write register b upper (twbu) timer write register c lower (twcl) timer write register c upper (twcu) r: w: r/w: $090 read only write only read/write data (464 digits) v = 2 (bank = 2) notes: 1. 2. $011 $012 w w r r 17 18 timer read register d lower (trdl) timer read register d upper (trdu) timer write register d lower (twdl) timer write register d upper (twdu) $084 w timer mode register d1 (tmd1) r/w r/w timer d (trdl/twdl) (trdu/twdu) timer mode register c2 (tmc2) $015 $016 r a/d data register lower (adrl) $017 $024 $025 $026 $027 $028 $029 $02a $02b $018 $019 $01a $01b $01c $01d $01e $01f $3ff a/d data register upper (adru) lcd control register (lcr) lcd mode register (lmr) lcd output register 1 (lor1) lcd output register 2 (lor2) lcd output register 3 (lor3) r w w w w w w w w port mode register b (pmrb) port mode register c (pmrc) detection edge select register 1 (esr1) detection edge select register 2 (esr2) serial mode register b (smrb) system clock select register (ssr) not used not used port r4 dcr (dcr4) port r5 dcr (dcr5) port r6 dcr (dcr6) port r7 dcr (dcr7) w w w w w w w w $03e $02c $02d $02e $02f $031 $030 r/w r/w r/w tg mode register (tgm) tg control register (tgc) w w *2 *1 ram address ram address figure 2 ram memory map
hd404629r series 13 bit 3 bit 2 bit 1 bit 0 imta (im of timer a) ifta (if of timer a) im1 (im of int 1 ) if1 (if of int 1 ) imtc (im of timer c) iftc (if of timer c) imtb (im of timer b) iftb (if of timer b) imad (im of a/d) ifad (if of a/d) imtd (im of timer d) iftd (if of timer d) $000 $001 $002 $003 interrupt control bits area im0 (im of int 0 ) if0 (if of int 0 ) rsp (reset sp bit) ie (interrupt enable flag) icsf (input capture status flag) im3 (im of int 3 ) if3 (if of int 3 ) im2 (im of int 2 ) if2 (if of int 2 ) ims (im of serial interface) ifs (if of serial interface) im4 (im of int 4 ) if4 (if of int 4 ) $020 $021 $022 $023 register flag area dton (direct transfer on flag) adsf (a/d start flag) wdon (watchdog on flag) lson (low speed on flag) icef (input capture error flag) rame (ram enable flag) not used if: im: ie: sp: interrupt request flag interrupt mask interrupt enable flag stack pointer bit 3 bit 2 bit 1 bit 0 figure 3 configuration of interrupt control bits and register flag areas ie im lson if icsf icef rame rsp wdon adsf not used dton sem/semd rem/remd tm/tmd allowed allowed allowed not executed allowed allowed not executed allowed inhibited allowed not executed inhibited allowed inhibited allowed not executed in active mode allowed allowed used in subactive mode not executed not executed inhibited note: wdon is reset by mcu reset or by stopc enable for stop mode cancellation. the rem or remd instuction must not be executed for adsf during a/d conversion. dton is always reset in active mode. if the tm or tmd instruction is executed for the inhibited bits or non-existing bits, the value in st becomes invalid. figure 4 usage limitations of ram bit manipulation instructions
hd404629r series 14 $000 $003 pmra $004 smra $005 srl $006 sru $007 tma $008 tmb1 $009 trbl/twbl $00a trbu/twbu $00b mis $00c tmci $00d trcl/twcl $00e trcu/twcu $00f tmdi $010 trdl/twdl $011 trdu/twdu $012 tmb2 $013 tmc2 $014 tmd2 $015 amr $016 adrl $017 adru $018 tgm $019 tgc $01a lcr $01b lmr $01c lor1 $01d lor2 $01e lor3 $01f $020 $023 pmrb $024 pmrc $025 esr1 $026 esr2 $027 smrb $028 ssr $029 dcd0 $02c dcd1 $02d dcd2 $02e dcr0 $030 dcr1 $031 dcr2 $032 dcr3 $033 dcr4 $034 dcr5 $035 dcr6 $036 dcr7 $037 v $03f bit 3 bit 2 bit 1 interrupt control bits area not used not used r2 2 /si r2 3 /so serial transmit clock speed selection serial data register (lower digit) serial data register (upper digit) clock source setting (timer a) clock source setting (timer b) timer b register (lower digit) timer b register (upper digit) r2 3 /so pmos control interrupt frame period selection clock source setting (timer c) timer c register (lower digit) timer c register (upper digit) clock source setting (timer d) timer d register (lower digit) timer d register (upper digit) not used not used timer-b output mode selection not used timer-c output mode setting timer-d output mode setting not used analog channel selection a/d data register (lower digit) a/d data register (upper digit) not used lcd duty cycle selection lcd input clock source selection r3 3 /seg4 r4 3 /seg8 not used r3 2 /seg3 r4 2 /seg7 r7/seg17?0 r3 1 /seg2 r4 1 /seg6 r6/seg13?6 r3 0 /seg1 r4 0 /seg5 r5/seg9?2 register flag area r0 1 /int 2 r2 0 /evnd int 2 detection edge selection int 4 detection edge selection int 3 detection edge selection evnd detection edge selection not used not used not used port d 3 dcr port d 7 dcr not used port d 2 dcr port d 6 dcr not used port d 1 dcr port d 5 dcr port d 9 dcr port d 0 dcr port d 4 dcr port d 8 dcr not used port r0 3 dcr port r1 3 dcr port r2 3 dcr port r3 3 dcr port r4 3 dcr port r5 3 dcr port r6 3 dcr port r7 3 dcr port r0 2 dcr port r1 2 dcr port r2 2 dcr port r3 2 dcr port r4 2 dcr port r5 2 dcr port r6 2 dcr port r7 2 dcr port r0 1 dcr port r1 1 dcr port r2 1 dcr port r3 1 dcr port r4 1 dcr port r5 1 dcr port r6 1 dcr port r7 1 dcr port r0 0 dcr port r1 0 dcr port r2 0 dcr port r3 0 dcr port r4 0 dcr port r5 0 dcr port r6 0 dcr port r7 0 dcr not used not used not used bank 0 to bank 2 selection 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. r0 2 /int 3 d 10 / stopc r0 3 /int 4 d 11 / int 0 r0 0 /int 1 r1 3 /evnb r2 1 /sck bit 0 clock select 1 * 2 * 3 * 2 * 2 * 4 * 5 * 8 * 9 * 10 * 11 * 12 * 13 * 14 * timer-a/time-base auto-reload on/off pull-up mos control input capture selection a/d conversion time tonec output control toner output control display on/off in watch mode lcd power switch lcd display on/off so idle h/l setting transmit clock source selection 32-khz oscillation stop setting 32-khz oscillation division ratio notes: tonec output frequency toner output frequency dtmf enable not used 6 * 7 * ram address figure 5 special function register area
hd404629r series 15 memory register (mr) area ($040?04f): consisting of 16 addresses, this area (mr0?r15) can be accessed by register-register instructions (lamr and xmra). the structure is shown in figure 6. memory registers $040 $041 $042 $043 $044 $045 $046 $047 $048 $049 $04a $04b $04c $04d $04e $04f $3c0 $3ff mr(0) mr(1) mr(2) mr(3) mr(4) mr(5) mr(6) mr(7) mr(8) mr(9) level 16 level 15 level 14 level 13 level 12 level 11 level 10 level 9 level 8 level 7 level 6 level 5 level 4 level 3 level 2 level 1 mr(10) mr(11) mr(12) mr(13) mr(14) mr(15) pc pc pc pc pc pc pc pc pc pc pc pc st pc ca pc 10 3 13 9 6 2 12 8 5 1 11 7 4 0 bit 3 bit 2 bit 1 bit 0 pc ?c : st: status flag ca: carry flag program counter 13 stack area 0 $3fc $3fd $3fe $3ff figure 6 configuration of memory registers and stack area, and stack position
hd404629r series 16 lcd data area ($050?083): used for storing 52-digit lcd data which is automatically output to lcd segments as display data. data 1 lights the corresponding lcd segment; data 0 extinguishes it. refer to the lcd description for details. data area ($090?3bf): 464 digits from $090 to $25f have three banks, which can be selected by setting the bank register (v: $03f). before accessing this area, set the bank register to the required value (figure 7). the area from $260 to $3bf is accessed without setting the bank register. bit initial value read/write bit name 3 not used 2 not used 0 0 r/w v0 1 0 r/w v1 v1 0 1 v0 0 1 0 1 bank area selection bank 0 is selected bank 1 is selected bank 2 is selected not used note: after reset, the value in the bank register is 0, and therefore bank 0 is selected. if v1 = 1 and v0 = 1, no bank is selected, and the operation is not guaranteed. bank register (v: $03f) figure 7 bank register (v) stack area ($3c0?3ff): used for saving the contents of the program counter (pc), status flag (st), and carry flag (ca) at subroutine call (cal or call instruction) and for interrupts. this area can be used as a 16-level nesting subroutine stack in which one level requires four digits. the data to be saved and the save conditions are shown in figure 6. the program counter is restored by either the rtn or rtni instruction, but the status and carry flags can only be restored by the rtni instruction. any unused space in this area is used for data storage.
hd404629r series 17 functional description registers and flags the mcu has nine registers and two flags for cpu operations. they are shown in figure 8 and described below. 30 30 30 30 30 30 0 0 0 13 95 1 (b) (a) (w) (x) (y) (spx) (spy) (ca) (st) (pc) (sp) 1111 accumulator b register w register x register y register spx register spy register carry status program counter initial value: $0000, r/w not possible stack pointer initial value: $3ff, r/w not possible 0 0 initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: 1, r/w not possible figure 8 registers and flags accumulator (a) and b register (b): a and b are 4-bit registers, and are used to hold the results of alu (arithmetic and logical unit) operations and to transfer data between memory, i/o ports, and other registers. w register (w), x register (x), and y register (y): w is a 2-bit register and x and y are 4-bit registers. these registers are used in ram register indirect addressing. the y register is also used in d port addressing.
hd404629r series 18 spx register (spx) and spy register (spy): the spx and spy registers are 4-bit registers used to supplement the x and y registers. carry flag (ca): ca is a 1-bit flag that stores alu overflow generated by an arithmetic operation. ca is set to 1 when an overflow is generated, and is cleared to 0 after operations in which no overflow occurred. ca is also affected by the carry set/carry clear instructions (sec and rec), and by the rotate with carry instructions (rotl and rotr). during interrupt handling, ca is saved on the stack, and is restored from the stack by the rtni instruction. status flag (st): st is a 1-bit flag that stores the results of arithmetic instructions, compare instructions, and bit test instructions, and is used as the branch condition for the br, brl, cal, and call conditional branch instructions. the contents of the st flag are held until the next arithmetic, compare, bit test, or conditional branch instruction is executed. after the execution of a conditional branch instruction, the value of st is set to 1 without regard to the condition. during interrupt handling, st is saved on the stack, and is restored from the stack by the rtni instruction. program counter (pc): the pc is a 14-bit counter that indicates the rom address of the next instruction the cpu will execute. stack pointer (sp): the sp is a 10-bit register that indicates the ram address of the next stack frame in the stack area. the sp is initialized to $3ff by a reset. the sp is decremented by 4 by a subroutine call or by interrupt handling, and is incremented by 4 when the saved data has been restored by a return instruction. the upper 4 bits of the sp are fixed at 1111; the maximum number of stack levels is thus 16. in addition to the reset method described above, the sp can also be initialized to $3ff by clearing the reset stack pointer (rsp) in the interrupt control bits area with a ram bit manipulation instruction, i.e., rem or remd. reset the mcu is reset by inputting a high-level voltage to the reset pin. at power-on or when stop mode is cancelled, reset must be high for at least one t rc to enable the oscillator to stabilize. during operation, reset must be high for at least two instruction cycles. initial values after mcu reset are listed in table 1.
hd404629r series 19 table 1 initial values after mcu reset item abbr. initial value contents program counter (pc) $0000 indicates program execution point from start address of rom area status flag (st) 1 enables conditional branching stack pointer (sp) $3ff stack level 0 interrupt interrupt enable flag (ie) 0 inhibits all interrupts flags/mask interrupt request flag (if) 0 indicates there is no interrupt request interrupt mask (im) 1 prevents (masks) interrupt requests i/o port data register (pdr) all bits 1 enables output at level 1 data control register (dcd0, dcd1) all bits 0 turns output buffer off (to high impedance) (dcd2) - - 00 (dcr0, ?cr7) all bits 0 port mode register a (pmra) - - 00 refer to description of port mode register a port mode register b (pmrb) 0000 refer to description of port mode register b port mode register c bits 3, 1, 0 (pmrc3, pmrc1, pmrc0) 000 refer to description of port mode register c detection edge select register 1 (esr1) 0000 disables edge detection detection edge select register 2 (esr2) 0000 disables edge detection timer/ timer mode register a (tma) 0000 refer to description of timer mode register a counters, timer mode register b1 (tmb1) 0000 refer to description of timer mode register b1 serial timer mode register b2 (tmb2) - - 00 refer to description of timer mode register b2 interface timer mode register c1 (tmc1) 0000 refer to description of timer mode register c1 timer mode register c2 (tmc2) - 000 refer to description of timer mode register c2 timer mode register d1 (tmd1) 0000 refer to description of timer mode register d1 timer mode register d2 (tmd2) 0000 refer to description of timer mode register d2 serial mode register a (smra) 0000 refer to description of serial mode register a serial mode register b (smrb) - - x0 refer to description of serial mode register b prescaler s (pss) $000 prescaler w (psw) $00 timer counter a (tca) $00 timer counter b (tcb) $00 timer counter c (tcc) $00 timer counter d (tcd) $00
hd404629r series 20 table 1 initial values after mcu reset (cont) item abbr. initial value contents timer/ counters, timer write register b (twbu, twbl) $x0 serial interface timer write register c (twcu, twcl) $x0 timer write register d (twdu, twdl) $x0 octal counter (oc) 000 a/d a/d mode register (amr) 00 - 0 refer to description of a/d mode register a/d data register (adrl, adru) $80 refer to description of a/d data register lcd lcd control register (lcr) - 000 refer to description of lcd control register lcd mode register (lmr) 0000 refer to description of lcd duty-cycle/clock control register lcd output register 1 (lor1) 0000 sets r-port/lcd segment pins to r port mode lcd output register 2 (lor2) 0000 lcd output register 3 (lor3) - 000 dtmf tone generator mode register (tgm) 0000 refer to description of tone generator mode register tone generator control register (tgc) 000 - refer to description of tone generator control register bit registers low speed on flag (lson) 0 refer to description of operating modes watchdog timer on flag (wdon) 0 refer to description of timer c a/d start flag (adsf) 0 refer to description of a/d converter direct transfer on flag (dton) 0 refer to description of operating modes input capture status flag (icsf) 0 refer to description of timer d input capture error flag (icef) 0 refer to description of timer d others miscellaneous register (mis) 0000 refer to description of operating modes, i/o, and serial interface system clock select register (ssr) 0000 refer to description of operating modes, oscillation circuits, and dtmf generator bank register (v) - - 00 refer to description of ram memory map notes: 1. the statuses of other registers and flags after mcu reset are shown in the following table. 2. x indicates invalid value. ?indicates that the bit does not exist.
hd404629r series 21 item abbr. status after cancel- lation of stop mode by stopc input status after cancel- lation of stop mode by reset input status after all other types of reset carry flag (ca) pre-stop-mode values are not guaranteed; pre-mcu-reset values accumulator (a) values must be initialized by program are not guaranteed; val- b register (b) ues must be initialized by w register (w) program x/spx register (x/spx) y/spy register (y/spy) serial data register (srl, sru) ram pre-stop-mode values are retained ram enable flag (rame) 1 0 0 port mode register c bit 2 (pmrc2) pre-stop-mode values are retained 00 system clock select register bit 3 (ssr3) interrupts the mcu has 11 interrupt sources: five external signals ( int 0 , int 1 , int 2 eint 4 ), four timer/ counters (timers a, b, c, and d), serial interface, and a/d converter. an interrupt request flag (if), interrupt mask (im), and vector address are provided for each interrupt source, and an interrupt enable flag (ie) controls the entire interrupt process. some vector addresses are shared by two different interrupts. they are timer b and int 2 , timer c and int 3 , timer d and int 4 , and a/d converter and serial interface interrupts. so the type of request that has occurred must be checked at the beginning of interrupt processing. interrupt control bits and interrupt processing: locations $000 to $003 and $022 to $023 in ram are reserved for the interrupt control bits which can be accessed by ram bit manipulation instructions. the interrupt request flag (if) cannot be set by software. mcu reset initializes the interrupt enable flag (ie) and the if to 0 and the interrupt mask (im) to 1. a block diagram of the interrupt control circuit is shown in figure 9, interrupt priorities and vector addresses are listed in table 2, and interrupt processing conditions for the 11 interrupt sources are listed in table 3. an interrupt request occurs when the if is set to 1 and the im is set to 0. if the ie is 1 at that point, the interrupt is processed. a priority programmable logic array (pla) generates the vector address assigned to that interrupt source. the interrupt processing sequence is shown in figure 10 and an interrupt processing flowchart is shown in figure 11. after an interrupt is acknowledged, the previous instruction is completed in the first cycle. the ie is reset in the second cycle, the carry, status, and program counter values are pushed onto the stack
hd404629r series 22 during the second and third cycles, and the program jumps to the vector address to execute the instruction in the third cycle. program the jmpl instruction at each vector address, to branch the program to the start address of the interrupt program, and reset the if by a software instruction within the interrupt program. table 2 vector addresses and interrupt priorities reset/interrupt priority vector address reset, stopc * $0000 int 0 1 $0002 int 1 2 $0004 timer a 3 $0006 timer b, int 2 4 $0008 timer c, int 3 5 $000a timer d, int 4 6 $000c a/d, serial 7 $000e note: * the stopc interrupt request is valid only in stop mode.
hd404629r series 23 ie ifo imo if1 im1 ifta imta iftb imtb iftc imtc iftd imtd $ 000,0 $ 000,2 $ 000,3 $ 001,0 $ 001,1 $ 001,2 $ 001,3 $ 002,0 $ 002,1 $ 002,2 $ 002,3 $ 003,0 $ 003,1 priority controller vector address note: $m,n is ram address $m, bit number n. ifad imad $ 003,2 $ 003,3 int 0 interrupt int 1 interrupt timer a interrupt timer b interrupt timer c interrupt timer d interrupt a/d interrupt if2 im2 if3 im3 if4 im4 $ 022,0 $ 022,1 $ 022,2 $ 022,3 $ 023,0 $ 023,1 ifs ims $ 023,2 $ 023,3 int 2 interrupt int 3 interrupt int 4 interrupt serial interrupt interrupt request figure 9 interrupt control circuit
hd404629r series 24 table 3 interrupt processing and activation conditions interrupt source interrupt cuntrol bit int 0 int 1 timer a timer b or int 2 timer c or int 3 timer d or int 4 a/d or serial i e 1 111 1 1 1 if0 . im0 1 000 0 0 0 if1 . im1 * 100 0 0 0 ifta . imta **10000 iftb . imtb + if2 . im2 * **1 00 0 iftc . imtc + if3 . im3 * *** 10 0 iftd . imtd + if4 . im4 * *** * 1 0 ifad . imad + ifs . ims * *** * * 1 note: bits marked * can be either 0 or 1. their values have no effect on operation. instruction cycles 123456 instruction execution ie reset interrupt acceptance execution of jmpl instruction at vector address execution of instruction at start address of interrupt routine vector address generation note: * * stacking the stack is accessed and the ie reset after the instruction is executed, even if it is a 2-cycle instruction. figure 10 interrupt processing sequence
hd404629r series 25 power on reset = 1? reset mcu interrupt request? execute instruction pc (pc) + 1 ? pc $0002 ? pc $0004 ? pc $0006 ? pc $0008 ? pc $000a ? pc $000e ? ie = 1? accept interrupt ie 0 stack (pc) stack (ca) stack (st) ? int 0 interrupt? int 1 interrupt? timer-a interrupt? timer-b/int 2 interrupt? no yes no yes no yes yes yes yes yes yes no no no no ? ? ? (a/d, serial interrupt) pc $000c ? timer-d/int 4 interrupt? yes no no timer-c/int 3 interrupt? figure 11 interrupt processing flowchart
hd404629r series 26 interrupt enable flag (ie: $000, bit 0): controls the entire interrupt process. it is reset by the interrupt processing and set by the rtni instruction, as listed in table 4. table 4 interrupt enable flag (ie: $000, bit 0) ie interrupt enabled/disabled 0 disabled 1 enabled external interrupts ( int 0 , int 1 , int 2 ?nt 4 ): five external interrupt signals. external interrupt request flags (if0?f4: $000, $001, $022, $023): if0 and if1 are set at the falling edge of signals input to int 0 and int 1 , and if2?f4 are set at the rising or falling edge of signals input to int 2 ?nt 4 , as listed in table 5. the int 2 ?nt 4 interrupt edges are selected by the detection edge select registers (esr1, esr2: $026, $027) as shown in figures 12 and 13. table 5 external interrupt request flags (if0?f4: $000, $001, $022, $023) if0?f4 interrupt request 0n o 1 yes bit initial value read/write bit name 3 0 w esr13 2 0 w esr12 0 0 w esr10 1 0 w esr11 detection edge selection register 1 (esr1: $026) esr11 0 1 esr10 0 1 0 1 int 2 detection edge no detection falling-edge detection rising-edge detection double-edge detection esr13 0 1 esr12 0 1 0 1 int 3 detection edge no detection falling-edge detection rising-edge detection double-edge detection note: both falling and rising edges are detected. * * * figure 12 detection edge selection register 1 (esr1)
hd404629r series 27 bit initial value read/write bit name 3 0 w esr23 2 0 w esr22 0 0 w esr20 1 0 w esr21 detection edge selection register 2 (esr2: $027) esr21 0 1 esr20 0 1 0 1 int 4 detection edge no detection falling-edge detection rising-edge detection double-edge detection esr23 0 1 esr22 0 1 0 1 evnd detection edge no detection falling-edge detection rising-edge detection double-edge detection note: both falling and rising edges are detected. ** * figure 13 detection edge selection register 2 (esr2) external interrupt masks (im0?m4: $000, $001, $022, $023): prevent (mask) interrupt requests caused by the corresponding external interrupt request flags, as listed in table 6. table 6 external interrupt masks (im0?m4: $000, $001, $022, $023) im0?m4 interrupt request 0 enabled 1 disabled (masked) timer a interrupt request flag (ifta: $001, bit 2): set by overflow output from timer a, as listed in table 7. table 7 timer a interrupt request flag (ifta: $001, bit 2) ifta interrupt request 0n o 1 yes
hd404629r series 28 timer a interrupt mask (imta: $001, bit 3): prevents (masks) an interrupt request caused by the timer a interrupt request flag, as listed in table 8. table 8 timer a interrupt mask (imta: $001, bit 3) imta interrupt?equest 0 enabled 1 disabled (masked) timer b interrupt request flag (iftb: $002, bit 0): set by overflow output from timer b, as listed in table 9. table 9 timer b interrupt request flag (iftb: $002, bit 0) iftb interrupt request 0n o 1 yes timer b interrupt mask (imtb: $002, bit 1): prevents (masks) an interrupt request caused by the timer b interrupt request flag, as listed in table 10. table 10 timer b interrupt mask (imtb: $002, bit 1) imtb interrupt request 0 enabled 1 disabled (masked) timer c interrupt request flag (iftc: $002, bit 2): set by overflow output from timer c, as listed in table 11. table 11 timer c interrupt request flag (iftc: $002, bit 2) iftc interrupt request 0n o 1 yes
hd404629r series 29 timer c interrupt mask (imtc: $002, bit 3): prevents (masks) an interrupt request caused by the timer c interrupt request flag, as listed in table 12. table 12 timer c interrupt mask (imtc: $002, bit 3) imtc interrupt request 0 enabled 1 disabled (masked) timer d interrupt request flag (iftd: $003, bit 0): set by overflow output from timer d, or by the rising or falling of signals input to evnd when the input capture function is used, as listed in table?3. table 13 timer d interrupt request flag (iftd: $003, bit 0) iftd interrupt request 0n o 1 yes timer d interrupt mask (imtd: $003, bit 1): prevents (masks) an interrupt request caused by the timer d interrupt request flag, as listed in table 14. table 14 timer d interrupt mask (imtd: $003, bit 1) imtd interrupt request 0 enabled 1 disabled (masked) serial interrupt request flag (ifs: $023, bit 2): set when data transfer is completed or when data transfer is suspended, as listed in table 15. table 15 serial interrupt request flag (ifs: $023, bit 2) ifs interrupt request 0n o 1 yes
hd404629r series 30 serial interrupt mask (ims: $023, bit 3): prevents (masks) an interrupt request caused by the serial interrupt request flag, as listed in table 16. table 16 serial interrupt mask (ims: $023, bit 3) ims interrupt request 0 enabled 1 disabled (masked) a/d interrupt request flag (ifad: $003, bit 2): set at the completion of a/d conversion, as listed in table 17. table 17 a/d interrupt request flag (ifad: $003, bit 2) ifad interrupt?equest 0n o 1 yes a/d interrupt mask (imad: $003, bit 3): prevents (masks) an interrupt request caused by the a/d interrupt request flag, as listed in table 18. table 18 a/d interrupt mask (imad: $003, bit 3) imad interrupt request 0 enabled 1 disabled (masked)
hd404629r series 31 operating modes the mcu has five operating modes as shown in table 19. the operations in each mode are listed in tables 20 and 21. transitions between operating modes are shown in figure 14. active mode: all mcu functions operate according to the clock generated by the system oscillator osc 1 and osc 2 . table 19 operating modes and clock status mode name active standby stop watch subactive *2 activation method reset cancellation, interrupt request, stopc cancellation in stop mode, stop/sby instruction in subactive mode (when direct transfer is selected) sby instruction stop instruction when tma3 = 0 stop instruction when tma3 = 1 int 0 or timer a interrupt request from watch mode status system oscillator op op stopped stopped stopped subsystem oscillator op op op*1 op op cancellation method reset input, stop/sby instruction reset input, interrupt request reset input, stopc input in stop mode reset input, int 0 or timer a interrupt request reset input, stop/sby instruction notes: op implies in operation. 1. operating or stopping the oscillator can be selected by setting bit 3 of the system clock select register (ssr: $029). 2. subactive mode is an optional function; specify it on the function option list.
hd404629r series 32 table 20 operations in low-power dissipation modes function stop mode watch mode standby mode subactive mode *2 cpu reset retained retained op ram retained retained retained op timer a reset op op op timer b reset stopped op op timer c reset stopped op op timer d reset stopped op op serial interface reset stopped *3 op op a/d reset stopped op stopped lcd reset op *4 op op dtmf reset reset stopped reset i/o reset *1 retained retained op notes: op implies in operation. 1. output pins are at high impedance. 2. subactive mode is an optional function specified on the function option list. 3. transmission/reception is activated if a clock is input in external clock mode. however, interrupts stop. 4. when a 32-khz clock source is used. table 21 i/o status in low-power dissipation modes output input standby mode, watch mode stop mode active mode, subactive mode d 0 ? 9 retained high impedance input enabled d 10 ? 11 input enabled r0?7 retained or output of peripheral functions high impedance input enabled
hd404629r series 33 reset by reset input or by watchdog timer f osc : f x : cpu : clk : per : oscillate oscillate stop f cyc f cyc f osc : f x : cpu : clk : per : oscillate oscillate stop f w f cyc f osc : f x : cpu : clk : per : oscillate oscillate f cyc f cyc f cyc f osc : f x : cpu : clk : per : oscillate oscillate f cyc f w f cyc f osc : f x : cpu : clk : per : stop oscillate f sub f w f sub f osc : f x : cpu : clk : per : stop stop stop stop stop f osc : f x : cpu : clk : per : stop oscillate stop f w stop f osc : f x : cpu : clk : per : stop oscillate stop f w stop standby mode stop mode (tma3 = 0, ssr3 = 1) watch mode subactive mode (tma3 = 1) (tma3 = 1, lson = 0) (tma3 = 1, lson = 1) sby interrupt sby interrupt stop int 0 , timer a * stop 1. interrupt source 2. stop/sby (dton = 1, lson = 0) 3. stop/sby (dton = 0, lson = 0) 4. stop/sby (dton = don? care, lson = 1) f osc : f x : f cyc : f sub : f w : lson: dton: main oscillation frequency suboscillation frequency for time-base f osc /4 f x /8 or f x /4 (software selectable) f x /8 cpu operating clock timer a operating clock clock for peripheral functions (except timer a) low speed on flag direct transfer on flag active mode notes: cpu : clk : per : f osc : f x : cpu : clk : per : stop oscillate stop stop stop (tma3 = 0, ssr3 = 0) reset1 reset2 rame = 0 rame = 1 int 0 , timer a (tma3 = 0) stop stopc stopc stop 1 * 2 * 3 * 1 * 4 figure 14 mcu status transitions
hd404629r series 34 standby mode: in standby mode, the oscillators continue to operate, but the clocks related to instruction execution stop. therefore, the cpu operation stops, but all ram and register contents are retained, and the d or r port status, when set to output, is maintained. peripheral functions such as interrupts, timers, and serial interface continue to operate. the power dissipation in this mode is lower than in active mode because the cpu stops. the mcu enters standby mode when the sby instruction is executed in active mode. standby mode is terminated by a reset input or an interrupt request. if it is terminated by reset input, the mcu is reset as well. after an interrupt request, the mcu enters active mode and executes the next instruction after the sby instruction. if the interrupt enable flag is 1, the interrupt is then processed; if it is 0, the interrupt request is left pending and normal instruction execution continues. a flowchart of operation in standby mode is shown in figure 15. standby mode no yes no yes no yes * 1 no yes no yes * 1 no yes * 1 yes * 1 watch mode system clock oscillator started system clock oscillator started system reset interrupts enabled no yes if = 1, im = 0, ie = 1? reset = 1? if0 ?im0 = 1? if1 ?im1 = 1? ifta ? imta = 1? iftb ? imtb + if2 ? im2 = 1? iftc ? imtc + if3 ? im3 = 1? iftd ? imtd + if4 ? im4 = 1? no yes * 1 ifad ? imad + ifs ? ims = 1? no stop mode reset = 1? stopc = 0? rame = 1 rame = 0 yes yes no no next instruction execution next instruction execution note: 1. only when clearing from standby mode figure 15 mcu operation flowchart
hd404629r series 35 stop mode: in stop mode, all mcu operations stop and ram data is retained. therefore, the power dissipation in this mode is the least of all modes. the osc 1 and osc 2 oscillator stops. for the x1 and x2 oscillator to operate or stop can be selected by setting bit 3 of the system clock select register (ssr: $029; operating: ssr3 = 0, stop: ssr3 = 1) (figure 27). the mcu enters stop mode if the stop instruction is executed in active mode when bit 3 of timer mode register a (tma: $008) is set to 0 (tma3 = 0) (figure 44). stop mode is terminated by a reset input or a stopc input as shown in figure 16. reset or stopc must be applied for at least one t rc to stabilize oscillation (refer to the ac characteristics section). when the mcu restarts after stop mode is cancelled, all ram contents before entering stop mode are retained, but the accuracy of the contents of the accumulator, b register, w register, x/spx register, y/spy register, carry flag, and serial data register cannot be guaranteed. stop mode oscillator internal clock stop instruction execution (at least equal to oscillator stabilization time t rc ) t res reset stopc figure 16 timing of stop mode cancellation watch mode: in watch mode, the clock function (timer a) using the x1 and x2 oscillator and the lcd function operate, but other function operations stop. therefore, the power dissipation in this mode is the second least to stop mode, and this mode is convenient when only clock display is used. in this mode, the osc 1 and osc 2 oscillator stops, but the x1 and x2 oscillator operates. the mcu enters watch mode if the stop instruction is executed in active mode when tma3 = 1, or if the stop or sby instruction is executed in subactive mode. watch mode is terminated by a reset input or a timer-a/ int 0 interrupt request. for details of reset input, refer to the stop mode section. when terminated by a timer-a/ int 0 interrupt request, the mcu enters active mode if lson = 0, or subactive mode if lson = 1. after an interrupt request is generated, the time required to enter active mode is t rc for a timer a interrupt, and t x ?where t + t rc < t x < 2t + t rc ) for an int 0 interrupt, as shown in figures 17 and 18. operation during mode transition is the same as that at standby mode cancellation (figure 15).
hd404629r series 36 subactive mode: the osc 1 and osc 2 oscillator stops and the mcu operates with a clock generated by the x1 and x2 oscillator. in this mode, functions except the a/d conversion operate. however, because the operating clock is slow, the power dissipation becomes low, next to watch mode. the cpu instruction execution speed can be selected as 244 m s or 122 m s by setting bit 2 (ssr2) of the system clock select register (ssr: $029). note that the ssr2 value must be changed in active mode. if the value is changed in subactive mode, the mcu may malfunction. when the stop or sby instruction is executed in subactive mode, the mcu enters either watch or active mode, depending on the statuses of the low speed on flag (lson: $020, bit 0) and the direct transfer on flag (dton: $020, bit 3). subactive mode is an optional function that the user must specify on the function option list. interrupt frame: in watch and subactive modes, f clk is applied to timer a and the int 0 i circuit. prescaler w and timer a operate as the time-base and generate the timing clock for the interrupt frame. three interrupt frame lengths (t) can be selected by setting the miscellaneous register (mis: $00c) (figure 18). in watch and subactive modes, the timer-a/ int 0 interrupt is generated synchronously with the interrupt frame. the interrupt request is generated synchronously with the interrupt strobe timing except during transition to active mode. the falling edge of the int 0 signal is input asynchronously with the interrupt frame timing, but it is regarded as input synchronously with the second interrupt strobe clock after the falling edge. an overflow and interrupt request in timer a is generated synchronously with the interrupt strobe timing.
hd404629r series 37 t rc t t x t t: t : interrupt frame period oscillation stabilization period rc (during the transition from watch mode to active mode only) interrupt strobe int 0 interrupt request generation active mode watch mode active mode oscillation stabilization period note: if the time from the fall of the int 0 signal until the interrrupt is accepted and active mode is entered is designated tx, then tx will be in the following range: t + t rc t x 2t + t rc figure 17 interrupt frame
hd404629r series 38 direct transition from subactive mode to active mode: available by controlling the direct transfer on flag (dton: $020, bit 3) and the low speed on flag (lson: $020, bit 0). the procedures are described below: set lson to 0 and dton to 1 in subactive mode. execute the stop or sby instruction. the mcu automatically enters active mode from subactive mode after waiting for the mcu internal processing time and oscillation stabilization time (figure 19). notes: 1. the dton flag can be set only in subactive mode. it is always reset in active mode. 2. the transition time (t d ) from subactive mode to active mode: t rc < t d < t + t rc bit initial value read/write bit name 3 0 w mis3 2 0 w mis2 0 0 w mis0 1 0 w mis1 miscellaneous register (mis: $00c) mis1 0 mis0 t * 0 0.24414 ms t rc 0.12207 ms 0.24414 ms 7.8125 ms 31.25 ms oscillation circuit conditions external clock input ceramic oscillator crystal oscillator 0 1 1 1 0 1 15.625 ms 62.5 ms not used not used notes: 1. 2. values of t and t rc when a 32.768-khz crystal oscillator is used to pins x1 and x2. the value is applied only when direct transfer operation is used. buffer control. refer to figure 41. mis3 mis2 1 * 1 * 2 figure 18 miscellaneous register (mis) subactive mode interrupt strobe direct transfer completion timing mcu internal processing time oscillation stabilization time active mode t t t rc t: t : t : rc d d stop/sby instruction execution (set lson = 0, dton = 1) interrupt frame length oscillation stabilization period direct transition time figure 19 direct transition timing
hd404629r series 39 stop mode cancellation by stopc : the mcu enters active mode from stop mode by inputting stopc as well as by reset. in either case, the mcu starts instruction execution from the starting address (address 0) of the program. however, the value of the ram enable flag (rame: $021, bit 3) differs between cancellation by stopc and by reset. when stop mode is cancelled by reset, rame = 0; when cancelled by stopc , rame = 1. reset can cancel all modes, but stopc is valid only in stop mode; stopc input is ignored in other modes. therefore, when the program requires to confirm that stop mode has been cancelled by stopc (for example, when the ram contents before entering stop mode is used after transition to active mode), execute the test instruction to the ram enable flag (rame) at the beginning of the program. mcu operation sequence: the mcu operates in the sequence shown in figures 20 to 22. it is reset by an asynchronous reset input, regardless of its status. the low-power mode operation sequence is shown in figure 22. with the ie flag cleared and an interrupt flag set together with its interrupt mask cleared, if a stop/sby instruction is executed, the instruction is cancelled (regarded as an nop) and the following instruction is executed. before executing a stop/sby instruction, make sure all interrupt flags are cleared or all interrupts are masked. power on reset = 1 ? rame = 0 reset mcu mcu operation cycle no yes figure 20 mcu operating sequence (power on)
hd404629r series 40 mcu operation cycle if = 1? instruction execution sby/stop instruction? pc next location pc vector address low-power mode operation cycle ie 0 stack (pc), (ca), (st) im = 0 and ie = 1? ? ? ? yes no no yes yes no if: im: ie: pc: ca: st: ? interrupt request flag interrupt mask interrupt enable flag program counter carry flag status flag figure 21 mcu operating sequence (mcu operation cycle)
hd404629r series 41 stop/sby instruction if = 1 and im = 0? hardware nop execution ? pc (pc)+1 ? pc (pc)+1 mcu operation cycle standby/watch mode if = 1 and im = 0? hardware nop execution instruction execution stop mode no yes ie = 0 yes no yes note: * refer to figure 15, flowchart for exiting low power modes, for if and im operation. stopc = 0? rame = 1 reset mcu no no yes * interrupt service routine figure 22 mcu operating sequence (low-power mode operation)
hd404629r series 42 notes: 1. when watch or subactive mode on hd404629r series/hd4074629 is used and the lcd function is off in that mode, the watch mode or subactive mode current is larger, and consequently the following settings should be made. perform the following writes in the order shown before the transition to watch mode (before execution of the stop instruction): write $0 to lcr write $3 to lmr also, when returning to active mode from watch mode or subactive mode, perform the following writes in the order shown: write a value appropriate to the conditions of use to lmr write a value appropriate to the conditions of use to lcr a sample programming flowchart for the above procedures is shown in figure 23. . . . lmr lcr . . . initialization routine include these operations . . . lcr = $0 lmr = $3 . . . main routine stop instruction watch mode or transition to subactive mode . . . lmr lcr . . . set appropriate values for active mode int or timer a interrupt processing routine 0 after the mcu enters active mode again set appropriate values for active mode figure 23 programming flowchart (lcd display off in watch or subactive mode)
hd404629r series 43 notes: 2. when the mcu is in watch mode or subactive mode, if the high level period before the falling edge of i nt 0 is shorter than the interrupt frame, i nt 0 is not detected. also, if the low level period after the falling edge of i nt 0 is shorter than the interrupt frame, i nt 0 is not detected. edge detection is shown in figure 24. the level of the int 0 signal is sampled by a sampling clock. when this sampled value changes to low from high, a falling edge is detected. in figure 25, the level of the i nt 0 signal is sampled by an interrupt frame. in (a) the sampled value is low at point a, and also low at point b. therefore, a falling edge is not detected. in (b), the sampled value is high at point a, and also high at point b. a falling edge is not detected in this case either. when the mcu is in watch mode or subactive mode, keep the high level and low level period of int 0 longer than interrupt frame. high low int sampling 0 low figure 24 edge detection a: low b: low int interrupt frame 0 a: high b: high int interrupt frame 0 (a) high level period (b) low level period figure 25 sampling example
hd404629r series 44 internal oscillator circuit a block diagram of the clock generation circuit is shown in figure 26. as shown in table 22, a ceramic oscillator can be connected to osc 1 and osc 2 , and a 32.768-khz oscillator can be connected to x1 and x2. the system oscillator can also be operated by an external clock. bit 0 and 1 (ssr1) of the system clock select register (ssr: $029) must be set according to the frequency of the oscillator connected to osc 1 and osc 2 (figure 27). note: if the system clock select register (ssr: $029) setting does not match the oscillator frequency, dtmf generator and subsystems using the 32.768-khz oscillation will malfunction. osc 2 osc 1 x1 x2 system clock oscillator sub- system clock oscillator 1/4 division circuit timing generation circuit system clock selection circuit cpu with rom, ram, registers, flags, and i/o internal peripheral module interrupts (other than timer a) timer a interrupt clock time-base clock selection circuit 1/8 or 1/4 division circuit timing generator circuit timing generation circuit 1/8 division circuit f w f sub t subcyc lson tma3 bit f cyc t cyc f osc f x t wcyc cpu per clk note: * * 1/8 or 1/4 division ratio can be selected by setting bit 2 of the system clock select register (ssr: $029). figure 26 clock generation circuit
hd404629r series 45 bit initial value read/write bit name 3 0 w ssr3 2 0 w ssr2 0 0 w ssr0 1 0 w ssr1 system clock select register (ssr: $029) ssr2 0 1 ratio selection f sub = f x /8 f sub = f x /4 ssr3 0 1 32-khz oscillation stop oscillation operates in stop mode oscillation stops in stop mode 32-khz oscillation division ssr1 0 0 1 1 system clock selection 400 khz 800 khz 2 mhz 4 mhz ssr0 0 1 0 1 note: ssr3 is cleared only by a reset input. ssr3 will not be cleared by a stopc input during stop mode, and will retain its value. ssr3 will also not be cleared upon entering stop mode. figure 27 system clock select register (ssr) d 0 gnd x2 x1 reset osc 2 osc 1 test av ss gnd figure 28 typical layouts of crystal and ceramic oscillator
hd404629r series 46 table 22 oscillator circuit examples circuit configuration circuit constants external clock operation external oscillator osc open 1 osc 2 ceramic oscillator (osc 1 , osc 2 ) osc 2 c 1 2 c osc 1 r f ceramic oscillator gnd ceramic oscillator: csb400p22 (murata) csb400p (murata) r f = 1 mw 20% c1 = c2 = 220 pf 5% ceramic oscillator: csb800j122 (murata), csb800j (murata) r f = 1 mw 20% c 1 = c 2 = 220 pf 5% ceramic oscillator: csa2.00mg (murata) r f = 1 mw 20% c 1 = c 2 = 30 pf 20% ceramic oscillator: csa4.00mg (murata) r f = 1 mw 20% c 1 = c 2 = 30 pf 20% crystal oscillator (osc 1 , osc 2 ) osc 1 c 1 2 c osc 2 crystal oscillator gnd l s c r s r f c 0 osc 1 osc 2 r f = 1 mw 20% c 1 = c 2 = 10 to 22pf 20% crystal : equivalent circuit at left c 0 =7pf max r s = 100w max f = 400khz, 800khz, 2mhz, 4mhz crystal oscillator (x1, x2) x1 c 1 2 c x2 crystal oscillator gnd l s c r s c 0 x1 x2 crystal oscillator: 32.768 khz: mx38t (nippon denpa) c 1 = c 2 = 20 pf 20% r s : 14 kw c 0 : 1.5 pf
hd404629r series 47 notes: 1. circuit constants differ by the different types of crystal oscillators, ceramic oscillators, and with the stray capacitance of the board, so consult the manufacturer of the oscillator to determine the circuit parameters. 2. the wiring between the osc 1 , osc 2 (x1 and x2 pins), and the other elements should be as short as possible, and must not cross other wiring. refer to figure 28. 3. if not using a 32.768-khz crystal oscillator, fix the x1 pin to v cc and leave the x2 pin open. input/output the mcu has 42 input/output pins (d 0 ? 9 , r0 0 ?7 3 ) and 2 input pins (d 10 , d 11 ). the features are described below. ten pins (d 0 ? 9 ) are high-current input/output pins. the d 10 and d 11 , and r0 0 ?7 3 input/output pins are multiplexed with peripheral function pins such as for the timers or serial interface. for these pins, the peripheral function setting is done prior to the d or r port setting. therefore, when a peripheral function is selected for a pin, the pin function and input/output selection are automatically switched according to the setting. input or output selection for input/output pins and port or peripheral function selection for multiplexed pins are set by software. peripheral function output pins are cmos output pins. only the r2 3 /so pin can be set to nmos open- drain output by software. in stop mode, the mcu is reset, and therefore peripheral function selection is cancelled. input/output pins are in high-impedance state. each input/output pin has a built-in pull-up mos, which can be individually turned on or off by software. i/o buffer configuration is shown in figure 29, programmable i/o circuits are listed in table 23, and i/o pin circuit types are shown in table 24. table 23 programmable i/o circuits mis3 (bit 3 of mis) 0 1 dcd, dcr 0 1 0 1 pdr 010 10 101 cmos buffer pmos on on nmos on on pull-up mos on on note: ?indicates off status.
hd404629r series 48 mis3 input control signal v cc pull-up mos dcd, dcr pdr input data v cc hlt pull-up control signal buffer control signal output data figure 29 i/o buffer configuration table 24 circuit configurations of i/o pins i/o pin type circuit pins input/output pins v cc v cc pull-up control signal buffer control signal output data input data hlt mis3 dcd, dcr pdr input control signal d 0 ?d 9 r0 0 ?0 3 r1 0 ?1 3 r2 0 ?2 2 r3 0 ?3 3 r4 0 ?4 3 r5 0 ?5 3 r6 0 ?6 3 r7 0 ?7 3 v cc v cc pull-up control signal buffer control signal output data input data hlt mis3 dcr pdr input control signal mis2 r2 3 input pins input data input control signal d 10 , d 11
hd404629r series 49 table 24 circuit configurations of i/o pins (cont) i/o pin type circuit pins peripheral function pins input/output pins v cc v cc pull-up control signal output data input data hlt mis3 sck sck sck output pins v cc v cc pull-up control signal pmos control signal output data hlt mis3 so mis2 so v cc v cc pull-up control signal output data hlt mis3 tob, toc, tod tob, toc, tod input pins input data si, int 1 , etc v cc hlt mis3 pdr si, int 1 , int 2 , int 3 , int 4 , evnb , evnd input data int 0 , stopc int 0 , stopc notes: 1. the mcu is reset in stop mode, and peripheral function selection is cancelled. the hlt signal becomes low, and input/output pins enter high-impedance state. 2. the hlt signal is 1 in watch and subactive modes.
hd404629r series 50 d port (d 0 ? 11 ): consist of 10 input/output pins and 2 input pins addressed by one bit. d 0 ? 9 are high- current i/o pins, and d 10 and d 11 are input-only pins. pins d 0 ? 9 are set by the sed and sedd instructions, and reset by the red and redd instructions. output data is stored in the port data register (pdr) for each pin. all pins d 0 ? 11 are tested by the td and tdd instructions. the on/off statuses of the output buffers are controlled by d-port data control registers (dcd0?cd2: $02c?02e) that are mapped to memory addresses (figure 30). pins d 10 and d 11 are multiplexed with peripheral function pins s t op c and i nt 0 , respectively. the peripheral function modes of these pins are selected by bits 2 and 3 (pmrc2, pmrc3) of port mode register c (pmrc: $025) (figure 31). r ports (r0 0 ?7 3 ): 32 input/output pins addressed in 4-bit units. data is input to these ports by the lar and lbr instructions, and output from them by the lra and lrb instructions. output data is stored in the port data register (pdr) for each pin. the on/off statuses of the output buffers of the r ports are controlled by r-port data control registers (dcr0?cr7: $030?037) that are mapped to memory addresses (figure 30). pins r0 0 ?0 3 are multiplexed with peripheral pins int 1 ?nt 4 , respectively. the peripheral function modes of these pins are selected by bits 0? (pmrb0?mrb3) of port mode register b (pmrb: $024) (figure 32). pins r1 0 ?1 2 are multiplexed with peripheral pins tob, toc, and tod, respectively. the peripheral function modes of these pins are selected by bits 0 and 1 (tmb20, tmb21) of timer mode register b2 (tmb2: $013), bits 0? (tmc20?mc22) of timer mode register c2 (tmc2: $014), and bits 0? (tmd20?md23) of timer mode register d2 (tmd2: $015) (figures 33, 34, and 35). pins r1 3 and r2 0 are multiplexed with peripheral pins evnb and evnd, respectively. the peripheral function modes of these pins are selected by bits 0 and 1 (pmrc0, pmrc1) of port mode register c (pmrc: $025) (figure 31). pins r2 1 ?2 3 are multiplexed with peripheral pins sck , si, and so, respectively. the peripheral function modes of these pins are selected by bit 3 (smra3) of serial mode register a (smra: $005), and bits 0 and 1 (pmra0, pmra1) of port mode register a (pmra: $004), as shown in figures 36 and 37. ports r3 and r4 are multiplexed with segment pins seg1?eg8, respectively. the function modes of these pins can be selected by individual pins, by setting lcd output registers 1 and 2 (lor1, lor2: $01d, $01f) (figures 38 and 39). ports r5?7 are multiplexed with segment pins seg9?eg20, respectively. the function modes of these pins can be selected in 4-pin units by setting lcd output register 3 (lor3: $01f) (figure 40).
hd404629r series 51 bit initial value read/write bit name 3 0 w dcd03, 2 0 w dcd02, 0 0 w dcd00, 1 0 w dcd01, dcd0, dcd1 data control register (dcd0 to 2: $02c to $02e) (dcr0 to 7: $030 to $037) dcd13 dcd12 dcd10 dcd11 bit initial value read/write bit name 3 not used 2 not used 0 0 w dcd20 1 0 w dcd21 dcd2 bit initial value read/write bit name 3 0 w dcr03 2 0 w dcr02 0 0 w dcr00 1 0 w dcr01 dcr0 to dcr7 dcr73 dcr72 dcr70 dcr71 all bits cmos buffer on/off selection 0 off (high-impedance) 1o n correspondence between ports and dcd/dcr bits register name bit 3 bit 2 bit 1 bit 0 dcd0 d 3 d 2 d 1 d 0 dcd1 d 7 d 6 d 5 d 4 dcd2 d 9 d 8 dcr0 r0 3 r0 2 r0 1 r0 0 dcr1 r1 3 r1 2 r1 1 r1 0 dcr2 r2 3 r2 2 r2 1 r2 0 dcr3 r3 3 r3 2 r3 1 r3 0 dcr4 r4 3 r4 2 r4 1 r4 0 dcr5 r5 3 r5 2 r5 1 r5 0 dcr6 r6 3 r6 2 r6 1 r6 0 dcr7 r7 3 r7 2 r7 1 r7 0 figure 30 data control registers (dcd, dcr)
hd404629r series 52 bit initial value read/write bit name 3 0 w pmrc3 2 0 w pmrc2 0 0 w pmrc0 1 0 w pmrc1 port mode register c (pmrc: $025) pmrc0 0 1 r1 3 pmrc1 0 1 r2 0 /evnd mode selection r2 0 evnd r1 3 /evnb mode selection evnb pmrc2 0 1 d 10 stopc pmrc3 0 1 d 11 d 11 /int 0 mode selection int 0 d 10 /stopc mode selection note: pmrc2 is reset to 0 only by reset input. when stopc is input in stop mode, pmrc2 is not reset but retains its value. * * figure 31 port mode register c (pmrc) bit initial value read/write bit name 3 0 w pmrb3 2 0 w pmrb2 0 0 w pmrb0 1 0 w pmrb1 pmrb0 0 1 r0 0 /int 1 mode selection r0 0 int 1 port mode register b (pmrb: $024) pmrb1 0 1 r0 1 /int 2 mode selection r0 1 int 2 pmrb2 0 1 r0 2 /int 3 mode selection r0 2 int 3 pmrb3 0 1 r0 3 /int 4 mode selection r0 3 int 4 figure 32 port mode register b (pmrb)
hd404629r series 53 bit initial value read/write bit name 3 not used 2 not used 0 0 r/w tmb20 1 0 r/w tmb21 timer mode register b2 (tmb2: $013) tmb21 0 1 tmb20 0 1 0 1 r1 0 /tob mode selection r1 0 tob tob tob r1 0 port toggle output 0 output 1 output figure 33 timer mode register b2 (tmb2) bit initial value read/write bit name 3 not used 2 0 r/w tmc22 0 0 r/w tmc20 1 0 r/w tmc21 timer mode register c2 (tmc2: $014) tmc22 tmc20 0 1 0 1 0 1 0 1 tmc21 0 1 0 1 0 1 r1 1 /toc mode selection r1 1 toc toc toc toc r1 1 port toggle output 0 output 1 output not used pwm output figure 34 timer mode register c2 (tmc2)
hd404629r series 54 bit initial value read/write bit name 3 0 r/w tmd23 2 0 r/w tmd22 0 0 r/w tmd20 1 0 r/w tmd21 timer mode register d2 (tmd2: $015) tmd22 tmd20 0 1 0 1 0 1 0 1 tmd21 0 1 0 1 0 1 r1 2 /tod mode selection r1 2 tod tod tod tod r1 2 r1 2 port toggle output 0 output 1 output not used pwm output input capture (r1 2 port) tmd23 0 1 55 5 5 : don? care figure 35 timer mode register d2 (tmd2) bit initial value read/write bit name 3 0 w smra3 2 0 w smra2 0 0 w smra0 1 0 w smra1 serial mode register a (smra: $005) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 output output output output output output output input prescaler prescaler prescaler prescaler prescaler prescaler system clock external clock ?2048 ?512 ?128 ?32 ?8 ?2 prescaler division ratio smra2 smra0 smra1 clock source smra3 0 1 r2 1 /sck mode selection sck r2 1 sck figure 36 serial mode register a (smra)
hd404629r series 55 bit initial value read/write bit name 3 not used 2 not used 0 0 w pmra0 1 0 w pmra1 pmra0 0 1 r2 3 /so mode selection r2 3 so port mode register a (pmra: $004) pmra1 0 1 r2 2 /si mode selection r2 2 si figure 37 port mode register a (pmra) bit initial value read/write bit name 3 0 w lor13 2 0 w lor12 0 0 w lor10 1 0 w lor11 lcd output register 1 (lor1: $01d) lor12 0 1 r3 2 /seg3 mode selection r3 2 seg3 lor13 0 1 r3 3 /seg4 mode selection r3 3 seg4 lor10 0 1 r3 0 /seg1 mode selection r3 0 seg1 lor11 0 1 r3 1 /seg2 mode selection r3 1 seg2 figure 38 lcd output register 1 (lor1)
hd404629r series 56 bit initial value read/write bit name 3 0 w lor23 2 0 w lor22 0 0 w lor20 1 0 w lor21 lcd output register 2 (lor2: $01e) lor21 0 1 r4 1 /seg6 mode selection r4 1 seg6 lor20 0 1 r4 0 /seg5 mode selection r4 0 seg5 lor22 0 1 r4 2 /seg7 mode selection r4 2 seg7 lor23 0 1 r4 3 /seg8 mode selection r4 3 seg8 figure 39 lcd output register 2 (lor2) bit initial value read/write bit name 3 not used 2 0 w lor32 0 0 w lor30 1 0 w lor31 lcd output register 3 (lor3: $01f) lor31 0 1 r6 0 /seg13?6 3 /seg16 mode selection r6 0 to r6 3 seg13?eg16 lor30 0 1 r5 0 /seg9?5 3 /seg12 mode selection r5 0 to r5 3 seg9?eg12 lor32 0 1 r7 0 /seg17?7 3 /seg20 mode selection r7 0 to r7 3 seg17?eg20 figure 40 lcd output register 3 (lor3)
hd404629r series 57 pull-up mos transistor control: a program-controlled pull-up mos transistor is provided for each input/output pin other than input-only pins d 10 and d 11 . the on/off status of all these transistors is controlled by bit 3 (mis3) of the miscellaneous register (mis: $00c), and the on/off status of an individual transistor can also be controlled by the port data register (pdr) of the corresponding pin?nabling on/off control of that pin alone (table 23 and figure 41). the on/off status of each transistor and the peripheral function mode of each pin can be set independently. how to deal with unused i/o pins: i/o pins that are not needed by the user system (floating) must be connected to v cc to prevent lsi malfunctions due to noise. these pins must either be pulled up to v cc by their pull-up mos transistors or by resistors of about 100 k w . bit initial value read/write bit name 3 0 w mis3 2 0 w mis2 0 0 w mis0 1 0 w mis1 mis2 cmos buffer on/off selection for pin r2 3 /so miscellaneous register (mis: $00c) 0 1 on off refer to figure 18 in the operation modes section. t rc selection. mis3 0 1 pull-up mos on/off selection off on mis1 mis0 figure 41 miscellaneous register (mis)
hd404629r series 58 prescalers the mcu has the following two prescalers, s and w. the prescalers operating conditions are listed in table 25, and the prescalers output supply is shown in figure 42. the timers a? input clocks except external events, the serial transmit clock except the external clock, and the lcd circuit operating clock are selected from the prescaler outputs, depending on corresponding mode registers. prescaler operation prescaler s: 11-bit counter that inputs the system clock signal. after being reset to $000 by mcu reset, prescaler s divides the system clock. prescaler s keeps counting, except in watch and subactive modes and at mcu reset. prescaler w: five-bit counter that inputs the x1 input clock signal (32-khz crystal oscillation) divided by eight. after being reset to $00 by mcu reset, prescaler w divides the input clock. prescaler w can be reset by software. table 25 prescaler operating conditions prescaler input clock reset conditions stop conditions prescaler s system clock (in active and standby mode), subsystem clock (in subactive mode) mcu reset mcu reset, stop mode, watch mode prescaler w 32-khz crystal oscillation mcu reset, software mcu reset, stop mode subsystem clock prescaler w lcd timer a timer b timer c timer d serial system clock prescaler s clock selector figure 42 prescaler output supply
hd404629r series 59 timers the mcu has four timer/counters (a to d). timer a: free-running timer timer b: multifunction timer timer c: multifunction timer timer d: multifunction timer timer a is an 8-bit free-running timer. timers b? are 8-bit multifunction timers, whose functions are listed in table 26. the operating modes are selected by software. table 26 timer functions functions timer a timer b timer c timer d clock prescaler s available available available available source prescaler w available external event available available timer free-running available available available available functions time-base available event counter available available reload available available available watchdog available input capture available timer toggle available available available outputs 0 output available available available 1 output available available available pwm available available note: ?implies not available. timer a timer a functions: timer a has the following functions. free-running timer clock time-base the block diagram of timer a is shown in figure 43.
hd404629r series 60 1/4 1/2 32.768-khz oscillator system clock prescaler w (psw) selector selector prescaler s (pss) selector internal data bus timer a interrupt request flag (ifta) clock overflow timer counter a (tca) timer mode register a (tma) 3 2 f 1/2 tw cyc f tw cyc per 2 4 8 32 128 512 1024 2048 ? ? ? ? ? ? ? ? 2 8 16 32 ? ? ? ? w w data bus clock line signal line figure 43 block diagram of timer a timer a operations: free-running timer operation: the input clock for timer a is selected by timer mode register a (tma: $008). timer a is reset to $00 by mcu reset and incremented at each input clock. if an input clock is applied to timer a after it has reached $ff, an overflow is generated, and timer a is reset to $00. the overflow sets the timer a interrupt request flag (ifta: $001, bit 2). timer a continues to be incremented after reset to $00, and therefore it generates regular interrupts every 256 clocks. clock time-base operation: timer a is used as a clock time-base by setting bit 3 (tma3) of timer mode register a (tma: $008) to 1. the prescaler w output is applied to timer a, and timer a generates interrupts at the correct timing based on the 32.768-khz crystal oscillation. in this case, prescaler w and timer a can be reset to $00 by software. registers for timer a operation: timer a operating modes are set by the following registers. timer mode register a (tma: $008): four-bit write-only register that selects timer a? operating mode and input clock source as shown in figure 44.
hd404629r series 61 bit initial value read/write bit name 3 0 w tma3 2 0 w tma2 0 0 w tma0 1 0 w tma1 timer mode register a (tma: $008) 00 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 x pss pss pss pss pss pss pss pss psw psw psw psw operating mode timer a mode tma3 tma1 tma2 tma0 source prescaler 2048t cyc 1024t cyc 512t cyc 128t cyc 32t cyc 8t cyc 4t cyc 2t cyc input clock frequency 0 1 1 32t wcyc 16t wcyc 8t wcyc 2t wcyc 1/2t wcyc time-base mode 00 1 1 0 1 1 x : don? care note: 1. 2. 3. 4. t wcyc = 244.14 m s (when a 32.768-khz crystal oscillator is used) timer counter overflow output period (seconds) = input clock period (seconds) 256. if psw of tca reset is selected while the lcd is operating, lcd operation halts (power switch goes off and all seg and com pins are grounded). when an lcd is connected for display, the psw and tca reset periods must be set in the program to the minimum. the division ratio must not be modified during time-base mode operation, otherwise an overflow cycle error will occur. not used reset psw and tca figure 44 timer mode register a (tma) timer b timer b functions: timer b has the following functions. free-running/reload timer external event counter timer output operation (toggle, 0, and 1 outputs)
hd404629r series 62 the block diagram of timer b is shown in figure 45. 2 3 4 4 4 timer b ineterrupt request flag (iftb) (tcbl) (tcbu) timer read register bu (trbu) internal data bus timer read register bl (trbl) timer counter b timer counter b (twbl) (twbu) free-runnning/reload control timer mode register b1 (tmb1) timer output control timer mode register b2 (tmb2) data bus clock line signal line selector overflow prescaler s (pss) system clock ?2 ?4 ?8 ?32 ?128 ?512 ?2048 timer output control logic tob evnb f per figure 45 block diagram of timer b
hd404629r series 63 timer b operations: free-running/reload timer operation: the free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register b1 (tmb1: $009). timer b is initialized to the value set in timer write register b (twbl: $00a, twbu: $00b) by software and incremented by one at each clock input. if an input clock is applied to timer b after it has reached $ff, an overflow is generated. in this case, if the reload timer function is enabled, timer b is initialized to its initial value set in timer write register b; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. the overflow sets the timer b interrupt request flag (iftb: $002, bit 0). iftb is reset by software or mcu reset. refer to figure 3 and table 1 for details. external event counter operation: timer b is used as an external event counter by selecting external event input as input clock source. in this case, pin r1 3 / evnb must be set to evnb by port mode register c (pmrc: $025). timer b is incremented by one at each falling edge of signals input to pin evnb. the other operation is basically the same as the free-running/reload timer operation. timer output operation: the following three output modes can be selected for timer b by setting timer mode register b2 (tmb2: $013). ? toggle ? 0 output ? 1 output by selecting the timer output mode, pin r1 0 /tob is set to tob. the output from tob is reset low by mcu reset. ? toggle output: when toggle output mode is selected, the output level is inverted if a clock is input after timer b has reached $ff. by using this function and reload timer function, clock signals can be output at a required frequency for the buzzer. the output waveform is shown in figure 46. ? 0 output: when 0 output mode is selected, the output level is pulled low if a clock is input after timer b has reached $ff. note that this function must be used only when the output level is high. ? 1 output: when 1 output mode is selected, the output level is set high if a clock is input after timer b has reached $ff. note that this function must be used only when the output level is low.
hd404629r series 64 t (n + 1) t 256 t t (256 ?n) tmc13 = 0 the waveform is always fixed low when n = $ff. t: n: tmc13 = 1 input clock period to counter (figures 52 and 60) the value of the timer write register note: tmd13 = 0 tmd13 = 1 256 clock cycles 256 clock cycles free-running timer toggle output waveform (timers b, c, and d) pwm output waveform (timers c and d) (256 ?n) clock cycles (256 ?n) clock cycles reload timer figure 46 timer output waveform
hd404629r series 65 registers for timer b operation: by using the following registers, timer b operation modes are selected and the timer b count is read and written. ? timer mode register b1 (tmb1: $009) ? timer mode register b2 (tmb2: $013) ? timer write register b (twbl: $00a, twbu: $00b) ? timer read register b (trbl: $00a, trbu: $00b) ? port mode register c (pmrc: $025) timer mode register b1 (tmb1: $009): four-bit write-only register that selects the free-running/reload timer function, input clock source, and the prescaler division ratio as shown in figure 47. it is reset to $0 by mcu reset. writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register b1 write instruction. setting timer b? initialization by writing to timer write register b (twbl: $00a, twbu: $00b) must be done after a mode change becomes valid. bit initial value read/write bit name 3 0 w tmb13 2 0 w tmb12 0 0 w tmb10 1 0 w tmb11 timer mode register b1 (tmb1: $009) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2048t cyc 512t cyc 128t cyc 32t cyc 8t cyc 4t cyc 2t cyc tmb12 tmb10 tmb11 input clock period and input clock source r1 3 / evnb (external event input) tmb13 0 1 free-running/reload timer selection free-running timer reload timer figure 47 timer mode register b1 (tmb1)
hd404629r series 66 bit initial value read/write bit name 3 not used 2 not used 0 0 r/w tmb20 1 0 r/w tmb21 timer mode register b2 (tmb2: $013) tmb21 0 1 tmb20 0 1 0 1 r1 0 /tob mode selection r1 0 tob tob tob r1 0 port toggle output 0 output 1 output figure 48 timer mode register b2 (tmb2) timer mode register b2 (tmb2: $013): two-bit read/write register that selects the timer b output mode as shown in figure 48. it is reset to $0 by mcu reset. timer write register b (twbl: $00a, twbu: $00b): write-only register consisting of the lower digit (twbl) and the upper digit (twbu) as shown in figures 49 and 50. the lower digit is reset to $0 by mcu reset, but the upper digit value is invalid. timer b is initialized by writing to timer write register b. in this case, the lower digit (twbl) must be written to first, but writing only to the lower digit does not change the timer b value. timer b is initialized to the value in timer write register b at the same time the upper digit (twbu) is written to. when timer write register b is written to again and if the lower digit value needs no change, writing only to the upper digit initializes timer b. bit initial value read/write bit name 3 0 w twbl3 2 0 w twbl2 0 0 w twbl0 1 0 w twbl1 timer write register b (lower digit) (twbl: $00a) figure 49 timer write register b lower digit (twbl) bit initial value read/write bit name 3 undefined w twbu3 2 undefined w twbu2 0 undefined w twbu0 1 undefined w twbu1 timer write register b (upper digit) (twbu: $00b) figure 50 timer write register b upper digit (twbu) timer read register b (trbl: $00a, trbu: $00b): read-only register consisting of the lower digit (trbl) and the upper digit (trbu) that holds the count of the timer b upper digit (figures 51 and 52).
hd404629r series 67 the upper digit (trbu) must be read first. at this time, the count of the timer b upper digit is obtained, and the count of the timer b lower digit is latched to the lower digit (trbl). after this, by reading trbl, the count of timer b when trbu is read can be obtained. bit initial value read/write bit name 3 undefined r trbl3 2 undefined r trbl2 0 undefined r trbl0 1 undefined r trbl1 timer read register b (lower digit) (trbl: $00a) figure 51 timer read register b lower digit (trbl) bit initial value read/write bit name 3 undefined r trbu3 2 undefined r trbu2 0 undefined r trbu0 1 undefined r trbu1 timer read register b (upper digit) (trbu: $00b) figure 52 timer read register b upper digit (trbu) port mode register c (pmrc: $025): write-only register that selects r1 3 / evnb pin function as shown in figure 53. it is reset to $0 by mcu reset. bit initial value read/write bit name 3 0 w pmrc3 2 0 w pmrc2 0 0 w pmrc0 1 0 w pmrc1 pmrc1 0 1 r2 0 /evnd mode selection r2 0 evnd port mode register c (pmrc: $025) pmrc0 0 1 r1 3 /evnb mode selection r1 3 evnb pmrc3 0 1 d 11 /int 0 mode selection d 11 int 0 pmrc2 0 1 d 10 /stopc mode selection d 10 stopc figure 53 port mode register c (pmrc)
hd404629r series 68 timer c timer c functions: timer c has the following functions. free-running/reload timer watchdog timer timer output operation (toggle, 0, 1, and pwm outputs) the block diagram of timer c is shown in figure 54. (twcl) (twcu) ?2 ? 4 ? 8 ? 32 ? 128 ? 512 ? 1024 ? per 3 3 4 4 4 toc ? 2048 (tccl) (tccu) system reset signal watchdog on flag (wdon) timer output control logic system clock prescalers (pss) watchdog timer control logic timer c interrupt request flag (iftc) timer read register cl (trcl) timer read register cu (trcu) timer counter c timer write register c timer mode register c1 (tmc1) timer output control timer mode register c2 (tmc2) selector free-running/reload control internal data bus data bus clock line signal line figure 54 block diagram of timer c
hd404629r series 69 timer c operations: free-running/reload timer operation: the free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register c1 (tmc1: $00d). timer c is initialized to the value set in timer write register c (twcl: $00e, twcu: $00f) by software and incremented by one at each clock input. if an input clock is applied to timer c after it has reached $ff, an overflow is generated. in this case, if the reload timer function is enabled, timer c is initialized to its initial value set in timer write register c; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. the overflow sets the timer c interrupt request flag (iftc: $002, bit 2). iftc is reset by software or mcu reset. refer to figure 3 and table 1 for details. watchdog timer operation: timer c is used as a watchdog timer for detecting out-of-control program routines by setting the watchdog on flag (wdon: $020, bit 1) to 1. if a program routine runs out of control and an overflow is generated, the mcu is reset. program run can be controlled by initializing timer c by software before it reaches $ff. timer output operation: the following four output modes can be selected for timer c by setting timer mode register c2 (tmc2: $014). ? toggle ? 0 output ? 1 output ? pwm output by selecting the timer output mode, pin r1 1 /toc is set to toc. the output from toc is reset low by mcu reset. ? toggle output: the operation is basically the same as that of timer-b? toggle output. ? 0 output: the operation is basically the same as that of timer-b? 0 output. ? 1 output: the operation is basically the same as that of timer-b? 1 output. ? pwm output: when pwm output mode is selected, timer c provides the variable-duty pulse output function. the output waveform differs depending on the contents of timer mode register c1 (tmc1: $00d) and timer write register c (twcl: $00e, twcu: $00f). the output waveform is shown in figure 46.
hd404629r series 70 registers for timer c operation: by using the following registers, timer c operation modes are selected and the timer c count is read and written. ? timer mode register c1 (tmc1: $00d) ? timer mode register c2 (tmc2: $014) ? timer write register c (twcl: $00e, twcu: $00f) ? timer read register c (trcl: $00e, trcu: $00f) timer mode register c1 (tmc1: $00d): four-bit write-only register that selects the free-running/reload timer function, input clock source, and the prescaler division ratio as shown in figure 55. it is reset to $0 by mcu reset. writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register c1 write instruction. setting timer c? initialization by writing to timer write register c (twcl: $00e, twcu: $00f) must be done after a mode change becomes valid. bit initial value read/write bit name 3 0 w tmc13 2 0 w tmc12 0 0 w tmc10 1 0 w tmc11 timer mode register c1 (tmc1: $00d) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2048t cyc 1024t cyc 512t cyc 128t cyc 32t cyc 8t cyc 4t cyc 2t cyc tmc12 tmc10 tmc11 tmc13 0 1 free-running/reload timer selection free-running timer reload timer input clock period figure 55 timer mode register c1 (tmc1) timer mode register c2 (tmc2: $014): three-bit read/write register that selects the timer c output mode as shown in figure 56. it is reset to $0 by mcu reset. timer write register c (twcl: $00e, twcu: $00f): write-only register consisting of the lower digit (twcl) and the upper digit (twcu). the operation of timer write register c is basically the same as that of timer write register b (twbl: $00a, twbu: $00b). timer read register c (trcl: $00e, trcu: $00f): read-only register consisting of the lower digit (trcl) and the upper digit (trcu) that holds the count of the timer c upper digit. the operation of timer read register c is basically the same as that of timer read register b (trbl: $00a, trbu: $00b).
hd404629r series 71 bit initial value read/write bit name 3 not used 2 0 r/w tmc22 0 0 r/w tmc20 1 0 r/w tmc21 timer mode register c2 (tmc2: $014) tmc22 0 tmc21 r1 1 /toc mode selection r1 1 toc toc toc toc r1 1 port toggle output 0 output 1 output not used pwm output tmc20 0 1 0 1 0 1 0 1 0 1 10 1 figure 56 timer mode register c2 (tmc2) bit initial value read/write bit name 3 0 w twcl3 2 0 w twcl2 0 0 w twcl0 1 0 w twcl1 timer write register c (lower digit) (twcl: $00e) figure 57 timer write register c lower digit (twcl) bit initial value read/write bit name 3 undefined w twcu3 2 undefined w twcu2 0 undefined w twcu0 1 undefined w twcu1 timer write register c (upper digit) (twcu: $00f) figure 58 timer write register c upper digit (twcu)
hd404629r series 72 bit initial value read/write bit name 3 undefined r trcl3 2 undefined r trcl2 0 undefined r trcl0 1 undefined r trcl1 timer read register c (lower digit) (trcl: $00e) figure 59 timer read register c lower digit (trcl) bit initial value read/write bit name 3 undefined r trcu3 2 undefined r trcu2 0 undefined r trcu0 1 undefined r trcu1 timer read register c (upper digit) (trcu: $00f) figure 60 timer read register c upper digit (trcu)
hd404629r series 73 timer d timer d functions: timer d has the following functions. free-running/reload timer external event counter timer output operation (toggle, 0, 1, and pwm outputs) input capture timer the block diagram for each operation mode of timer d is shown in figures 61 and 62. timer d operations: free-running/reload timer operation: the free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register d1 (tmd1: $010). timer d is initialized to the value set in timer write register d (twdl: $011, twdu: $012) by software and incremented by one at each clock input. if an input clock is applied to timer d after it has reached $ff, an overflow is generated. in this case, if the reload timer function is enabled, timer d is initialized to its initial value set in timer write register d; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. the overflow sets the timer d interrupt request flag (iftd: $003, bit 0). iftd is reset by software or mcu reset. refer to figure 3 and table 1 for details. external event counter operation: timer d is used as an external event counter by selecting the external event input as an input clock source. in this case, pin r2 0 /evnd must be set to evnd by port mode register c (pmrc: $025). either falling or rising edge, or both falling and rising edges of input signals can be selected as the external event detection edge by detection edge select register 2 (esr2: $027). when both rising and falling edges detection is selected, the time between the falling edge and rising edge of input signals must be 2t cyc or longer. timer d is incremented by one at each detection edge selected by detection edge select register 2 (esr2: $027). the other operation is basically the same as the free-running/reload timer operation. timer output operation: the following four output modes can be selected for timer d by setting timer mode register d2 (tmd2: $015). ? toggle ? 0 output ? 1 output ? pwm output by selecting the timer output mode, pin r1 2 /tod is set to tod. the output from tod is reset low by mcu reset. ? toggle output: the operation is basically the same as that of timer-b? toggle output. ? 0 output: the operation is basically the same as that of timer-b? 0 output.
hd404629r series 74 ? 1 output: the operation is basically the same as that of timer-b? 1 output. ? pwm output: the operation is basically the same as that of timer-c? pwm output. input capture timer operation: the input capture timer counts the clock cycles between trigger edges input to pin evnd. either falling or rising edge, or both falling and rising edges of input signals can be selected as the trigger input edge by detection edge select register 2 (esr2: $027). when a trigger edge is input to evnd, the count of timer d is written to timer read register d (trdl: $011, trdu: $012), and the timer d interrupt request flag (iftd: $003, bit 0) and the input capture status flag (icsf: $021, bit 0) are set. timer d is reset to $00, and then incremented again. while icsf is set, if a trigger input edge is applied to timer d, or if timer d generates an overflow, the input capture error flag (icef: $021, bit 1) is set. icsf and icef are reset to 0 by mcu reset or by writing 0. by selecting the input capture operation, pin r1 2 /tod is set to r1 2 and timer d is reset to $00.
hd404629r series 75 (twdl) (twdu) ? 2 ? 4 ? 8 ? 32 ? 128 ? 512 ? 2048 2 3 3 4 4 4 tod ?er timer read register du (trdu) prescaler s (pss) selector timer mode register d1 (tmd1) edge detection logic evnd system clock edge detection control data bus clock line signal line edge detection selection register 2 (esr2) timer output control logic timer mode register d2 (tmd2) timer write register d free-running/reload control timer read register dl (trdl) timer d interrupt request flag (iftd) internal data bus (tcdl) (tcdu) timer counter d figure 61 block diagram of timer d (free-running/reload timer)
hd404629r series 76 2 3 4 4 evnd input capture status flag (icsf) input capture error flag (icef) timer d interrupt request flag (iftd) error control logic read signal edge detection logic system clock prescaler s (pss) selector timer read register d timer counter d (trdl) (trdu) (tcdl) (tcdu) input capture timer control overflow internal data bus timer mode register d2 (tmd2) data bus clock line signal line edge detection control edge detection selection register 2 (esr2) time mode register d1 (tmd1) ?2 ?4 ?8 ?32 ?128 ?512 ?2048 ?er figure 62 block diagram of timer d (input capture timer) registers for timer d operation: by using the following registers, timer d operation modes are selected and the timer d count is read and written. ? timer mode register d1 (tmd1: $010) ? timer mode register d2 (tmd2: $015) ? timer write register d (twdl: $011, twdu: $012) ? timer read register d (trdl: $011, trdu: $012)
hd404629r series 77 ? port mode register c (pmrc: $025) ? detection edge select register 2 (esr2: $027) timer mode register d1 (tmd1: $010): four-bit write-only register that selects the free-running/reload timer function, input clock source, and the prescaler division ratio as shown in figure 63. it is reset to $0 by mcu reset. writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register d1 (tmd1: $010) write instruction. setting timer d? initialization by writing to timer write register d (twdl: $011, twdu: $012) must be done after a mode change becomes valid. when selecting the input capture timer operation, select the internal clock as the input clock source. bit initial value read/write bit name 3 0 w tmd13 2 0 w tmd12 0 0 w tmd10 1 0 w tmd11 timer mode register d1 (tmd1: $010) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2048t cyc 512t cyc 128t cyc 32t cyc 8t cyc 4t cyc 2t cyc tmd12 tmd10 tmd11 input clock period and input clock source r2 0 /evnd (external event input) tmd13 0 1 free-running/reload timer selection free-running timer reload timer figure 63 timer mode register d1 (tmd1) timer mode register d2 (tmd2: $015): four-bit read/write register that selects the timer d output mode and input capture operation as shown in figure 64. it is reset to $0 by mcu reset. timer write register d (twdl: $011, twdu: $012): write-only register consisting of the lower digit (twdl) and the upper digit (twdu). the operation of timer write register d is basically the same as that of timer write register b (twbl: $00a, twbu: $00b). timer read register d (trdl: $011, trdu: $012): read-only register consisting of the lower digit (trdl) and the upper digit (trdu). the operation of timer read register d is basically the same as that of timer read register b (trbl: $00a, trbu: $00b). when the input capture timer operation is selected and if the count of timer d is read after a trigger is input, either the lower or upper digit can be read first.
hd404629r series 78 port mode register c (pmrc: $025): write-only register that selects r2 0 /evnd pin function as shown in figure 53. it is reset to $0 by mcu reset. detection edge select register 2 (esr2: $027): write-only register that selects the detection edge of signals input to pin evnd as shown in figure 69. it is reset to $0 by mcu reset. bit initial value read/write bit name 3 0 r/w tmd23 2 0 r/w tmd22 0 0 r/w tmd20 1 0 r/w tmd21 timer mode register d2 (tmd2: $015) tmd22 tmd20 0 1 0 1 0 1 0 1 tmd21 0 1 0 1 0 1 r1 2 /tod mode selection r1 2 tod tod tod tod r1 2 r1 2 port toggle output 0 output 1 output not used pwm output input capture (r1 2 port) tmd23 0 1 55 5 5 : don? care figure 64 timer mode register d2 (tmd2) bit initial value read/write bit name 3 0 w twdl3 2 0 w twdl2 0 0 w twdl0 1 0 w twdl1 timer write register d (lower digit) (twdl: $011) figure 65 timer write register d lower digit (twdl)
hd404629r series 79 bit initial value read/write bit name 3 undefined w twdu3 2 undefined w twdu2 0 undefined w twdu0 1 undefined w twdu1 timer write register d (upper digit) (twdu: $012) figure 66 timer write register d upper digit (twdu) bit initial value read/write bit name 3 undefined r trdl3 2 undefined r trdl2 0 undefined r trdl0 1 undefined r trdl1 timer read register d (lower digit) (trdl: $011) figure 67 timer read register d lower digit (trdl) bit initial value read/write bit name 3 undefined r trdu3 2 undefined r trdu2 0 undefined r trdu0 timer read register d (upper digit) (trdu: $012) 1 undefined r trdu1 figure 68 timer read register d upper digit (trdu)
hd404629r series 80 bit initial value read/write bit name 3 0 w esr23 2 0 w esr22 0 0 w esr20 1 0 w esr21 detection edge register 2 (esr2: $027) esr21 0 1 esr20 0 1 0 1 int 4 detection edge no detection falling-edge detection rising-edge detection double-edge detection esr23 0 1 esr22 0 1 0 1 evnd detection edge no detection falling-edge detection rising-edge detection double-edge detection note: both falling and rising edges are detected. ** * figure 69 detection edge select register 2 (esr2)
hd404629r series 81 note on use when using the timer output as pwm output, note the following point. from the update of the timer write register untill the occurrence of the overflow interrupt, the pwm output differs from the period and duty settings, as shown in table 27. the pwm output should therefore not be used until after the overflow interrupt following the update of the timer write register. after the overflow, the pwm output will have the set period and duty cycle. table 27 pwm output following update of timer write register pwm output mode timer write register is updated during high pwm output timer write register is updated during low pwm output free running timer write register rewrite (set value is n) timer write register rewrite (set value is n) interrupt request generated interrupt request generated t (255 ?n) t (n + 1) t (n' + 1) t (255 ?n) t (n + 1) reload timer write register rewrite (set value is n) timer write register rewrite (set value is n) interrupt request generated interrupt request generated t t (255 ?n) t t t (255 ?n) t
hd404629r series 82 serial interfaces the serial interface serially transfers and receives 8-bit data, and includes the following features. multiple transmit clock sources ? external clock ? internal prescaler output clock ? system clock output level control in idle states five registers, an octal counter, and a multiplexer are also configured for the serial interface as follows. ? serial data register (srl: $006, sru: $007) ? serial mode register a (smra: $005) ? serial mode register b (smrb: $028) ? miscellaneous register (mis: $00c) ? octal counter (oc) ? selector the block diagram of the serial interface is shown in figure 70.
hd404629r series 83 ?2 ?8 ?32 ?128 so sck si system clock per ?512 ?2048 1/2 1/2 serial interrupt request flag (ifs) octal counter (oc) idle control logic i/o control logic clock transfer control data bus clock line signal line serial mode register a (smra) serial mode register b (smrb) serial data register (srl/u) internal data bus selector selector prescalers (pss) figure 70 block diagram of serial interface
hd404629r series 84 serial interface operation selecting and changing the operating mode: table 28 lists the serial interface? operating modes. to select an operating mode, use one of these combinations of port mode register a (pmra: $004) and serial mode register a (smra: $005) settings; to change the operating mode, always initialize the serial interface internally by writing data to serial mode register a. note that the serial interface is initialized by writing data to serial mode register a. refer to the following serial mode register a section for details. pin setting: the r2 1 / sck pin is controlled by writing data to serial mode register a (smra: $005). the r2 2 /si and r2 3 /so pins are controlled by writing data to port mode register a (pmra: $004). refer to the following registers for serial interface section for details. transmit clock source setting: the transmit clock source is set by writing data to serial mode register a (smra: $005) and serial mode register b (smrb: $028). refer to the following registers for serial interface section for details. data setting: transmit data is set by writing data to the serial data register (srl: $006, sru: $007). receive data is obtained by reading the contents of the serial data register. the serial data is shifted by the transmit clock and is input from or output to an external system. the output level of the so pin is invalid until the first data is output after mcu reset, or until the output level control in idle states is performed. table 28 serial interface operating modes smra pmra bit 3 bit 1 bit 0 operating mode 1 0 0 continuous clock output mode 1 transmit mode 1 0 receive mode 1 transmit/receive mode transfer control: the serial interface is activated by the sts instruction. the octal counter is reset to 000 by this instruction, and it increments at the rising edge of the transmit clock. when the eighth transmit clock signal is input or when serial transmission/receive is discontinued, the octal counter is reset to 000, the serial interrupt request flag (ifs: $023, bit 2) is set, and the transfer stops. when the prescaler output is selected as the transmit clock, the transmit clock frequency is selected as 4t cyc to 8192t cyc by setting bits 2 to 0 (smra2?smra0) of serial mode register a (smra: $005) and bit 0 (smrb0) of serial mode register b (smrb: $028) as listed in table 29.
hd404629r series 85 table 29 serial transmit clock (prescaler output) smrb smra bit 0 bit 2 bit 1 bit 0 prescaler division ratio transmit clock frequency 0000 ? 2048 4096t cyc 1 ? 512 1024t cyc 10 ? 128 256t cyc 1 ? 32 64t cyc 100 ? 8 16t cyc 1 ? 24t cyc 1000 ? 4096 8192t cyc 1 ? 1024 2048t cyc 10 ? 256 512t cyc 1 ? 64 128t cyc 100 ? 16 32t cyc 1 ? 48t cyc operating states: the serial interface has the following operating states; transitions between them are shown in figure 71. ? sts wait state ? transmit clock wait state ? transfer state ? continuous clock output state (only in internal clock mode) sts wait state: the serial interface enters sts wait state by mcu reset (00, 10 in figure 71). in sts wait state, the serial interface is initialized and the transmit clock is ignored. if the sts instruction is then executed (01, 11), the serial interface enters transmit clock wait state. transmit clock wait state: transmit clock wait state is between the sts execution and the falling edge of the first transmit clock. in transmit clock wait state, input of the transmit clock (02, 12) increments the octal counter, shifts the serial data register, and enters the serial interface in transfer state. however, note that if continuous clock output mode is selected in internal clock mode, the serial interface does not enter transfer state but enters continuous clock output state (17). the serial interface enters sts wait state by writing data to serial mode register a (smra: $005) (04, 14) in transmit clock wait state. transfer state: transfer state is between the falling edge of the first clock and the rising edge of the eighth clock. in transfer state, the input of eight clocks or the execution of the sts instruction sets the octal counter to 000, and the serial interface enters another state. when the sts instruction is executed (05, 15), transmit clock wait state is entered. when eight clocks are input, transmit clock wait state is entered (03) in external clock mode, and sts wait state is entered (13) in internal clock mode. in internal clock mode, the transmit clock stops after outputting eight clocks.
hd404629r series 86 in transfer state, writing data to serial mode register a (smra: $005) (06, 16) initializes the serial interface, and sts wait state is entered. if the state changes from transfer to another state, the serial interrupt request flag (ifs: $023, bit 2) is set by the octal counter that is reset to 000. continuous clock output state (only in internal clock mode): continuous clock output state is entered only in internal clock mode. in this state, the serial interface does not transmit/ receive data but only outputs the transmit clock from the sck pin. when bits 1 and 0 (pmra1, pmra0) of port mode register a (pmra: $004) are 00 in transmit clock wait state and if the transmit clock is input (17), the serial interface enters continuous clock output state. if serial mode register a (smra: $005) is written to in continuous clock output mode (18), sts wait state is entered. sts wait state (octal counter = 000, transmit clock disabled) transmit clock wait state (octal counter = 000) transfer state (octal counter = 000) mcu reset 00 smra write 04 sts instruction 01 transmit clock 02 8 transmit clocks 03 sts instruction (ifs 1) 05 ? smra write (ifs 1) 06 ? external clock mode sts wait state (octal counter = 000, transmit clock disabled) transmit clock wait state (octal counter = 000) transfer state (octal counter = 000) smra write 14 sts instruction 11 transmit clock 12 15 sts instruction (ifs 1) ? 8 transmit clocks 13 internal clock mode continuous clock output state (pmra 0, 1 = 00) smra write 18 transmit clock 17 16 note: refer to the operating states section for the corresponding encircled numbers. mcu reset 10 ? smra write (ifs 1) figure 71 serial interface state transitions output level control in idle states: in idle states, that is, sts wait state and transmit clock wait state, the output level of the so pin can be controlled by setting bit 1 (smrb1) of serial mode register b (smrb: $028) to 0 or 1. the output level control example is shown in figure 72. note that the output level cannot be controlled in transfer state.
hd404629r series 87
state mcu reset pmra write smra write smrb write srl, sru write sts instruction sck pin (input) so pin ifs idle idle idle idle sts wait state transmit clock wait state transfer state transmit clock wait state sts wait state port selection external clock selection output level control in idle states dummy write for state transition output level control in idle states data write for transmission undefined lsb msb flag reset at transfer completion external clock mode state mcu reset pmra write smra write smrb write srl, sru write sts instruction sck pin (output) so pin ifs sts wait state transfer state transmit clock wait state sts wait state port selection internal clock selection output level control in idle states data write for transmission output level control in idle states undefined lsb msb flag reset at transfer completion internal clock mode figure 72 example of serial interface operation sequence
hd404629r series 88 transmit clock error detection (in external clock mode): the serial interface will malfunction if a spurious pulse caused by external noise conflicts with a normal transmit clock during transfer. a transmit clock error of this type can be detected as shown in figure 73.
hd404629r series 89 transfer completion (ifs 1) interrupts inhibited ifs 0 smra write ifs = 1? transmit clock error processing normal termination ? ? yes no transmit clock error detection flowchart
transmit clock error detection procedure state sck pin (input) transmit clock wait state transfer state transfer state transmit clock wait state noise transfer state has been entered by the transmit clock error. when smra is written, ifs is set. flag set because octal counter reaches 000 flag reset at transfer completion smra write ifs 12 3 45678 figure 73 transmit clock error detection
hd404629r series 90 if more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse by noise, the octal counter reaches 000, the serial interrupt request flag (ifs: $023, bit 2) is set, and transmit clock wait state is entered. at the falling edge of the next normal clock signal, the transfer state is entered. after the transfer completion processing is performed and ifs is reset, writing to serial mode register a (smra: $005) changes the state from transfer to sts wait. at this time ifs is set again, and therefore the error can be detected. notes on use: initialization after writing to registers: if port mode register a (pmra: $004) is written to in transmit clock wait state or in transfer state, the serial interface must be initialized by writing to serial mode register a (smra: $005) again. serial interrupt request flag (ifs: $023, bit 2) set: if the state is changed from transfer to another by writing to serial mode register a (smra: $005) or executing the sts instruction during the first low pulse of the transmit clock, the serial interrupt request flag is not set. to set the serial interrupt request flag, serial mode register a write or sts instruction execution must be programmed to be executed after confirming that the sck pin is at 1, that is, after executing the input instruction to port r2. registers for serial interface the serial interface operation is selected, and serial data is read and written by the following registers. ? serial mode register a (smra: $005) ? serial mode register b (smrb: $028) ? serial data register (srl: $006, sru: $007) ? port mode register a (pmra: $004) ? miscellaneous register (mis: $00c) serial mode register a (smra: $005): this register has the following functions (figure 74). ? r2 1 / sck pin function selection ? transfer clock selection ? prescaler division ratio selection ? serial interface initialization serial mode register a (smra: $005) is a 4-bit write-only register. it is reset to $0 by mcu reset. a write signal input to serial mode register a (smra: $005) discontinues the input of the transmit clock to the serial data register and octal counter, and the octal counter is reset to 000. therefore, if a write is performed during data transfer, the serial interrupt request flag (ifs: $023, bit 2) is set. written data is valid from the second instruction execution cycle after the write operation, so the sts instruction must be executed at least two cycles after that.
hd404629r series 91 bit initial value read/write bit name 3 0 w smra3 2 0 w smra2 0 0 w smra0 1 0 w smra1 serial mode register a (smra: $005) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 smra2 smra0 smra1 smra3 0 1 r2 1 /sck mode selection r2 1 sck output output input clock source prescaler division ratio refer to table 29 sck prescaler system clock external clock figure 74 serial mode register a (smra) serial mode register b (smrb: $028): this register has the following functions (figure 75). ? prescaler division ratio selection ? output level control in idle states serial mode register b is a 2-bit write-only register. it cannot be written during data transfer. by setting bit 0 (smrb0) of this register, the prescaler division ratio is selected. only bit 0 (smrb0) can be reset to 0 by mcu reset. by setting bit 1 (smrb1), the output level of the so pin is controlled in idle states. the output level changes at the same time that smrb1 is written to.
hd404629r series 92 bit initial value read/write bit name 3 not used 2 not used 0 0 w smrb0 1 undefined w smrb1 smrb0 0 1 transmit clock division ratio prescaler output divided by 2 prescaler output divided by 4 serial mode register b (smrb: $028) smrb1 0 1 output level control in idle states low level high level figure 75 serial mode register b (smrb) serial data register (srl: $006, sru: $007): this register has the following functions (figures 76 and 77). ? transmission data write and shift ? receive data shift and read writing data in this register is output from the so pin, lsb first, synchronously with the falling edge of the transmit clock; data is input, lsb first, through the si pin at the rising edge of the transmit clock. input/output timing is shown in figure 78. data cannot be read or written during serial data transfer. if a read/write occurs during transfer, the accuracy of the resultant data cannot be guaranteed. bit initial value read/write bit name 3 undefined r/w sr3 2 undefined r/w sr2 0 undefined r/w sr0 1 undefined r/w sr1 serial data register (lower digit) (srl: $006) figure 76 serial data register (srl)
hd404629r series 93 bit initial value read/write bit name 3 undefined r/w sr7 2 undefined r/w sr6 0 undefined r/w sr4 1 undefined r/w sr5 serial data register (upper digit) (sru: $007) figure 77 serial data register (sru) lsb msb 12 345 678 transmit clock serial output data serial input data latch timing figure 78 serial interface output timing port mode register a (pmra: $004): this register has the following functions (figure 79). ? r2 2 /si pin function selection ? r2 3 /so pin function selection port mode register a (pmra: $004) is a 2-bit write-only register, and is reset to $0 by mcu reset. bit initial value read/write bit name 3 not used 2 not used 0 0 w pmra0 1 0 w pmra1 pmra0 0 1 r2 3 /so mode selection r2 3 so port mode register a (pmra: $004) pmra1 0 1 r2 2 /si mode selection r2 2 si figure 79 port mode register a (pmra)
hd404629r series 94 miscellaneous register (mis: $00c): this register has the following function (figure 80). ? r2 3 /so pin pmos control miscellaneous register (mis: $00c) is a 4-bit write-only register and is reset to $0 by mcu reset. bit initial value read/write bit name 3 0 w mis3 2 0 w mis2 0 0 w mis0 1 0 w mis1 miscellaneous register (mis: $00c) mis1 0 1 mis0 0 1 0 1 t rc 0.12207 ms 0.24414 ms 7.8125 ms 31.25 ms not used mis2 0 1 r2 3 /so pmos on/off selection on off mis3 0 1 pull-up mos on/off selection off on figure 80 miscellaneous register (mis) a/d converter the mcu has a built-in a/d converter that uses a successive approximation method with a resistor ladder. it can measure four analog inputs with 8-bit resolution. as shown in the block diagram of figure 81, the a/d converter has a 4-bit a/d mode register, a 1-bit a/d start flag, and a 4-bit plus 4-bit a/d data register.
hd404629r series 95 2 an 0 an 1 an 2 an 3 av cc av ss + a/d interrupt request flag (ifad) a/d mode register (amr) encoder conversion time control off in stop, watch, and subactive modes a/d control logic a/d start flag (adsf) data bus signal line resistance ladder a/d data register (adr) internal data bus selector comp figure 81 block diagram of a/d converter a/d mode register (amr: $016): four-bit write-only register which selects the a/d conversion period and indicates analog input pin information. bit 0 of the a/d mode register selects the a/d conversion period, and bits 3 and 2 select a channel, as shown in figure 82.
hd404629r series 96 bit initial value read/write bit name 3 0 w amr3 2 0 w amr2 0 0 w amr0 1 not used a/d mode register (amr: $016) amr0 0 1 conversion time 34t cyc 67t cyc amr3 0 0 1 1 amr2 0 1 0 1 analog input selection an 0 an 1 an 2 an 3 figure 82 a/d mode register (amr) a/d data register (adrl: $017, adru: $018): eight-bit read-only register consisting of a 4-bit lower digit and 4-bit upper digit. this register is not cleared by reset. after the completion of a/d conversion, the resultant eight-bit data is held in this register until the start of the next conversion (figures 83, 84, and 85). 3210 msb lsb 3210 bit 0 bit 7 adru: $018 adrl: $017 figure 83 a/d data registers (adru, adrl)
hd404629r series 97 bit initial value read/write bit name 3 0 r adrl3 2 0 r adrl2 0 0 r adrl0 1 0 r adrl1 a/d data register (lower digit) (adrl: $017) figure 84 a/d data register lower digit (adrl) bit initial value read/write bit name a/d data register (upper digit) (adru: $018) 2 0 r adru2 1 0 r adru1 0 0 r adru0 3 1 r adru3 figure 85 a/d data register upper digit (adru) a/d start flag (adsf: $020, bit 2): one-bit flag that initiates a/d conversion when set to 1. at the completion of a/d conversion, the converted data is stored in the a/d data register and the a/d start flag is cleared. refer to figure 86. bit initial value read/write bit name 3 0 r/w dton 2 0 r/w adsf 0 0 r/w lson 1 0 r/w wdon a/d start flag (adsf: $020, bit 2) 1 0 adsf (a/d start flag) a/d conversion started a/d conversion completed refer to the description of operating modes dton refer to the description of timers wdon refer to the description of operating modes lson figure 86 a/d start flag (adsf)
hd404629r series 98 note on use: use the sem and semd instructions to write data to the a/d start flag (adsf: $020, bit 2), but make sure that the a/d start flag is not written to during a/d conversion. data read from the a/d data register (adrl: $017, adru: $018) during a/d conversion cannot be guaranteed. the a/d converter does not operate in the stop, watch, and subactive modes because of the osc clock. during these low-power dissipation modes, current through the resistor ladder is cut off to decrease the power input. dtmf generation circuit the mcu provides a dual-tone multifrequency (dtmf) generation circuit. the dtmf signal consists of two sine waves to access the switching system. figure 87 shows the dtmf keypad and frequencies. each key enables tones to be generated corresponding to each frequency. figure 88 shows a block diagram of the dtmf circuit. the osc clock (400 khz, 800 khz, 2 mhz, or 4 mhz) is changed into four clock signals through the division circuit ( 1/2 , 1/5 , and 1/10). the dtmf circuit uses one of the four clock signals, which is selected by the system clock select register (ssr: $029) depending on the osc clock frequency. the dtmf circuit has transformed programmable dividers, sine wave counters, and control registers. the dtmf generation circuit is controlled by the following three registers. 123a 456b 789c * 0#d r1 (697 hz) r2 (770 hz) r3 (852 hz) r4 (941 hz) c1 (1,209 hz) c2 (1,336 hz) c3 (1,477 hz) c4 (1,633 hz) figure 87 dtmf keypad and frequencies
hd404629r series 99 sine wave counter d/a transforma- tion program divider feedback sine wave counter d/a transforma- tion program divider feedback toner vt ref tonec toner output control tonec output control 1/2 1/5 1/10 f osc tone generator control register (tgc) system clock selection register (ssr) 400 khz 2 2 2 selector tone generator mode register (tgm) internal data bus 800 khz 2 mhz 4 mhz 400 khz data bus clock line signal line figure 88 block diagram of dtmf circuit
hd404629r series 100 tone generator mode register (tgm: $019): four-bit write-only register, which controls output frequencies as shown in figure 89, and is reset to $0 by mcu reset. bit initial value read/write bit name 3 0 w tgm3 2 0 w tgm2 0 0 w tgm0 1 0 w tgm1 tone generator mode register (tgm: $019) tgm3 0 0 1 1 tgm2 0 1 0 1 tonec output frequencies f c1 (1,209 hz) f c2 (1,336 hz) f c3 (1,477 hz) f c4 (1,633 hz) tgm1 0 0 1 1 tgm0 0 1 0 1 toner output frequencies f r1 (697 hz) f r2 (770 hz) f r3 (852 hz) f r4 (941 hz) figure 89 tone generator mode register (tgm) tone generator control register (tgc: $01a): three-bit write-only register, which controls the start/stop of the dtmf signal output as shown in figure 90, and is reset to $0 by mcu reset. toner and tonec output can be independently controlled by bits 3 and 2 (tgc3, tgc2), and the dtmf circuit is controlled by bit 1 (tgc1) of this register. bit initial value read/write bit name 3 0 w tgc3 2 0 w tgc2 0 not used 1 0 w tgc1 tone generator control register (tgc: $01a) tgc1 0 1 dtmf enable bit dtmf disable dtmf enable tgc2 0 1 toner output control (row) no output toner output (active) tgc3 0 1 tonec output control (column) no output tonec output (active) figure 90 tone generator control register (tgc)
hd404629r series 101 system clock select register (ssr: $029): four-bit write-only register. this register must be set to the value specified in figure 91 depending on the frequency of the oscillator connected to the osc 1 and osc 2 pins. note that if the combination of the oscillation frequency and the value in this register is different from that specified in figure 91, the dtmf output frequencies will differ from the correct frequencies as listed in figure 89. bit initial value read/write bit name 3 0 w ssr3 2 0 w ssr2 0 0 w ssr0 1 0 w ssr1 system clock select register (ssr: $029) ssr1 0 0 1 1 system clock selection 400 khz 800 khz 2 mhz 4 mhz ssr0 0 1 0 1 ssr2 0 1 ratio selection f sub = f x /8 f sub = f x /4 ssr3 0 1 32-khz oscillation stop oscillation operates in stop mode oscillation stops in stop mode 32-khz oscillation division note: ssr3 is cleared only by a reset input. ssr3 will not be cleared by a stopc input during stop mode, and will retain its value. ssr3 will also not be cleared upon entering stop mode. figure 91 system clock select register (ssr)
hd404629r series 102 dtmf output: the sine waves of the row-group and column-group are individually converted in the d/a conversion circuit which provides a high-precision ladder resistance. the dtmf output pins (toner, tonec) transmit the sine waves of the row-group and column-group, respectively. figure 92 shows the tone output equivalent circuit. figure 93 shows the output waveform. one cycle of this wave consists of 32 slots. therefore, the output waveform is stable with little distortion. table 30 lists the frequency deviation of the mcu from standard dtmf signals. table 30 frequency deviation of the mcu from standard dtmf standard dtmf (hz) mcu (hz) deviation from standard (%) r1 697 694.44 ?.37 r2 770 769.23 ?.10 r3 852 851.06 ?.11 r4 941 938.97 ?.22 c1 1,209 1,212.12 0.26 c2 1,336 1,333.33 ?.20 c3 1,477 1,481.48 0.30 c4 1,633 1,639.34 0.39 note: this frequency deviation value does not include the frequency deviation due to the oscillator element. also note that in this case the ratio of the high level and low level widths in the oscillator waveform due to the oscillator element will be 50%:50%. vt gnd ref switch control toner tonec figure 92 tone output equivalent circuit
hd404629r series 103 vt gnd ref 12345678910111213141516171819202122232425262728293031 32 time slot figure 93 waveform of tone output
hd404629r series 104 lcd controller/driver the mcu has an lcd controller and driver which drive 4 common signal pins and 52 segment pins. the controller consists of a ram area in which display data is stored, a display control register (lcr: $01b), and a duty-cycle/clock-control register (lmr: $01c) (figure 94). four duty cycles and the lcd clock are programmable, and a built-in dual-port ram ensures that display data can be automatically transmitted to the segment signal pins without program intervention. if a 32-khz oscillation clock is selected as the lcd clock source, the lcd can even be used in watch mode, in which the system clock stops. internal lcd power supply switch 52 2 2 4 4 3 lcd mode register (lmr) 2 v cc v 1 v 2 v 3 gnd com1 com2 com3 com4 seg1 seg4 seg5 seg8 seg9 seg20 seg21 seg52 cl0 cl1 cl2 cl3 note: pin function switching circuit lcd power supply control circuit common signal output circuit lcd control register (lcr) lcd output register 1 (lor1) lcd output register 2 (lor2) lcd output register 3 (lor3) dual-port display ram (52 digits) display control display data duty selection clock internal data bus segment signal output circuit selector data bus clock line signal line pin control figure 94 block diagram of liquid crystal display control system
hd404629r series 105 lcd data area and segment data ($050?083): as shown in figure 95, each bit of the storage area corresponds to one of four duty cycles. if data is written to an area corresponding to a certain duty cycle, it is automatically output to the corresponding segments as display data. $060 $061 $062 $063 $064 $065 $066 $067 $068 $069 com4 com3 com2 com1 bit 3 bit 2 bit 1 bit 0 $050 $051 $052 $053 $054 $055 $056 $057 $058 $059 $05a $05b $05c $05d $05e $05f seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 bit 3 bit 2 bit 1 bit 0 $06a $06b $06c $06d $06e $06f $070 $071 $072 $073 $074 $075 $076 $077 $078 $079 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 seg40 seg41 seg42 $07a $07b $07c $07d $07e $07f $080 $081 $082 $083 com4 com3 com2 com1 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg43 seg44 seg45 seg46 seg47 seg48 seg49 seg50 seg51 seg52 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg17 seg18 seg19 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 seg40 seg41 seg42 seg43 seg44 seg45 seg46 seg47 seg48 seg49 seg50 seg51 seg52 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 seg40 seg41 seg42 seg43 seg44 seg45 seg46 seg47 seg48 seg49 seg50 seg51 seg52 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 seg40 seg41 seg42 seg43 seg44 seg45 seg46 seg47 seg48 seg49 seg50 seg51 seg52 ram address ram address figure 95 configuration of lcd ram area (for dual-port ram)
hd404629r series 106 lcd control register (lcr: $01b): three-bit write-only register which controls lcd blanking, on/off switching of the liquid-crystal display? power supply division resistor, and display in watch and subactive modes, as shown in figure 96. blank/display blank: segment signals are turned off, regardless of lcd ram data setting. display: lcd ram data is output as segment signals. power switch on/off off: the power switch is off. on: the power switch is on and v1 is v cc . watch/subactive mode display off: in watch and subactive modes, all common and segment pins are grounded and the liquid-crystal power switch is turned off. on: in watch and subactive modes, lcd ram data is output as segment signals. bit initial value read/write bit name 3 not used 2 0 w lcr2 0 0 w lcr0 1 0 w lcr1 lcd display control register (lcr: $01b) lcr1 0 1 power switch on/off off on lcr0 0 1 blank/display blank display 0 1 display on/off selection in watch and subactive modes lcr2 off on figure 96 lcd control register (lcr)
hd404629r series 107 lcd duty-cycle/clock control register (lmr: $01c): four-bit write-only register which selects the display duty cycle and lcd clock source, as shown in figure 97. the dependence of frame frequency on duty cycle is listed in table 31. bit initial value read/write bit name 3 0 w lmr3 2 0 w lmr2 0 0 w lmr0 1 0 w lmr1 lcd duty cycle/clock control register (lmr: $01c) lmr3 lmr2 input clock source selection lmr1 0 0 1 1 lmr0 0 1 0 1 duty cycle selection 1/4 duty 1/3 duty 1/2 duty static cl0 (32.768-khz duty/64: when 32.768-khz oscillation is used) 0 1 1 1 0 1 cl1 (f osc duty cycle/1024) cl2 (f osc duty cycle/8192) cl3 (refer to table 31) 00 figure 97 lcd duty-cycle/clock control register (lmr)
hd404629r series 108 table 31 lcd frame frequencies for different duty cycles frame frequencies duty cycle lmr3 lmr2 f osc = 400 khz f osc = 800 khz f osc = 2 mhz f osc = 4 mhz static 0 0 cl0 512 hz 1 cl1 390.6 hz 781.3 hz 1953 hz 3906 hz 1 0 cl2 48.8 hz 97.7 hz 244.1 hz 488.3 hz 1 cl3* 24.4 hz 48.8 hz 122.1 hz 244.1 hz 64 hz 1/2 0 0 cl0 256 hz 1 cl1 195.3 hz 390.6 hz 976.6 hz 1953 hz 1 0 cl2 24.4 hz 48.8 hz 122.1 hz 244.1 hz 1 cl3* 12.2 hz 24.4 hz 61 hz 122.1 hz 32 hz 1/3 0 0 cl0 170.7 hz 1 cl1 130.2 hz 260.4 hz 651 hz 1302 hz 1 0 cl2 16.3 hz 32.6 hz 81.4 hz 162.8 hz 1 cl3* 8.1 hz 16.3 hz 40.7 hz 81.4 hz 21.3 hz 1/4 0 0 cl0 128 hz 1 cl1 97.7 hz 195.3 hz 488.3 hz 976.6 hz 1 0 cl2 12.2 hz 24.4 hz 61 hz 122.1 hz 1 cl3* 6.1 hz 12.2 hz 30.5 hz 61 hz 16 hz note: * the division ratio depends on the value of bit 3 of timer mode register a (tma). upper value: when tma3 = 0, cl3 = f osc duty cycle/16384. lower value: when tma3 = 1, cl3 = 32.768 khz duty cycle/512.
hd404629r series 109 lcd output register 1 (lor1: $01d): write-only register used to specify ports r3 0 ?3 3 as pins seg1 seg4 by individual pins (figure 98). bit initial value read/write bit name 3 0 w lor13 2 0 w lor12 0 0 w lor10 1 0 w lor11 lcd output register 1 (lor1: $01d) lor10 0 1 r3 0 /seg1 mode selection r3 0 seg1 lor11 0 1 r3 1 /seg2 mode selection r3 1 seg2 lor12 0 1 r3 2 /seg3 mode selection r3 2 seg3 lor13 0 1 r3 3 /seg4 mode selection r3 3 seg4 figure 98 lcd output register 1 (lor1) lcd output register 2 (lor2: $01e): write-only register used to specify ports r4 0 ?4 3 as pins seg5 seg8 by individual pins (figure 99). bit initial value read/write bit name 3 0 w lor23 2 0 w lor22 0 0 w lor20 1 0 w lor21 lcd output register 2 (lor2: $01e) lor20 0 1 r4 0 /seg5 mode selection r4 0 seg5 lor21 0 1 r4 1 /seg6 mode selection r4 1 seg6 lor22 0 1 r4 2 /seg7 mode selection r4 2 seg7 lor23 0 1 r4 3 /seg8 mode selection r4 3 seg8 figure 99 lcd output register 2 (lor2)
hd404629r series 110 lcd output register 3 (lor3: $01f): write-only register used to specify ports r5?7 as pins seg9 seg20 in 4-pin units (figure 100). bit initial value read/write bit name 3 not used 2 0 w lor32 0 0 w lor30 1 0 w lor31 lcd output register 3 (lor3: $01f) lor30 0 1 r5 0 /seg9?5 3 /seg12 mode selection r5 0 -r5 3 seg9?eg12 lor31 0 1 r6 0 /seg13?6 3 /seg16 mode selection r6 0 -r6 3 seg13?eg16 lor32 0 1 r7 0 /seg17?7 3 /seg20 mode selection r7 0 -r7 3 seg17?eg20 figure 100 lcd output register 3 (lor3) large liquid-crystal panel drive and v lcd : to drive a large-capacity lcd, decrease the resistance of the built-in division resistors by attaching external resistors in parallel, as shown in figure 101. the size of these resistors cannot be simply calculated from the lcd load capacitance because the matrix configuration of the lcd complicates the paths of charge/discharge currents flowing through the capacitors?he resistance will also vary with lighting conditions. this size must be determined by trial- and-error, taking into account the power dissipation of the device using the lcd, but a resistance of 1 to 10 kw would usually be suitable. (another effective method is to attach capacitors of 0.1 to 0.3 m f.) always turn off the power switch (set bit 1 of the lcr to 0) before changing the liquid-crystal drive voltage (v lcd ).
hd404629r series 111 52 2 3 4 52 52 52 v cc v 2 v 3 gnd v 1 com1 seg1 to seg52 v cc v 2 v 3 gnd v 1 com1 com2 seg1 to seg52 v cc v 2 v 3 gnd v 1 com1 to com3 seg1 to seg52 v cc v 2 v 3 gnd v 1 com1 to com4 seg1 to seg52 v cc v lcd v cc v lcd v cc v lcd v cc v lcd r r r v (v ) cc 1 v 2 v 3 gnd r r r v (v ) cc 1 v 2 v 3 gnd c c c 6-digit lcd with sign . 13-digit lcd 17-digit lcd with sign 26-digit lcd . . . static drive 1/2 duty, 1/2 bias drive 1/3 duty, 1/3 bias drive 1/4 duty, 1/3 bias drive v v gnd cc lcd 3 3 1 figure 101 lcd connection examples
hd404629r series 112 ztat tm microcomputer with built-in programmable rom programming of built-in programmable rom the mcu can stop its function as an mcu in prom mode for programming the built-in prom. prom mode is set up by setting the test , m 0 , and m 1 terminals to ?ow?level and the reset terminal to ?igh?level. writing and reading specifications of the prom are the same as those for the commercial eprom27256. using a socket adapter for specific use of each product, programming is possible with a general-purpose prom writer. since an instruction of the hmcs400 series is 10 bits long, a conversion circuit is incorporated to adapt the general-purpose prom writer. this circuit splits each instruction into five lower bits and five higher bits to write from or read to two addresses. this enables use of a general-purpose prom. for instance, to write to a 16kword of built-in prom with a general-purpose prom writer, specify 32kbyte address ($0000-$7fff). notes: 1. when programming with a prom writer, set up each rom size to the address given in table b. if it is programmed erroneously to an address given in table 33 or later, check of writing of prom may become impossible. particularly, caution should be exercised in the case of a plastic package since reprogramming is impossible with it. set the data in unused addresses to $ff. 2. if the indexes of the prom writer socket, socket adapter and product are not aligned precisely, the product may break down due to overcurrent. be sure to check that they are properly set to the writer before starting the writing process. 3. two levels of program voltages (v pp ) are available for the prom: 12.5 v and 21 v. our product employs a v pp of 12.5 v. if a voltage of 21 v is applied, permanent breakdown of the product will result. the v pp of 12.5 v is obtained for the prom writer by setting it according to the intel 27258 specifications. writing/verification programming of the built-in program rom employs a high speed programming method. with this method, high speed writing is effected without voltage stress to the device or without damaging the reliability of the written data. for precautions for prom writing procedure, refer to section 2, "characteristics of ztat tm microcomputer's built-in programmable rom and precautions for its applications."
hd404629r series 113 table 32 selection of mode mode ce oe v pp o 0 ? 7 writing ?ow ?igh v pp data input verification ?igh ?ow v pp data output prohibition of programming ?igh ?igh v pp high impedance table 33 prom writer program address rom size address 8k $0000~$3fff 12k $0000~$5fff 16k $0000~$7fff
hd404629r series 114 programmable rom (hd4074629) the hd4074629 is a ztat tm microcomputer with built-in prom that can be programmed in prom mode. prom mode pin description pin no. mcu mode prom mode pin no. mcu mode prom mode fp-100b tfp-100b fp-100a pin name i/o pin name i/o fp-100b tfp-100b fp-100a pin name i/o pin name i/o 13a v cc v cc 24 26 d 10 / stopc i/o a 9 i 24a n 0 i 2527d 11 / int 0 i/o v pp 35a n 1 i 2628r0 0 / int 1 i/o gnd 46a n 2 i 2729r0 1 /int 2 i/o gnd 57a n 3 i 2830r0 2 /int 3 i/o 68a v ss gnd 29 31 r0 3 /int 4 i/o 79 test i gnd 30 32 r1 0 /tob i/o a 5 i 8 10 osc 1 iv cc 31 33 r1 1 /toc i/o a 6 i 9 11 osc 2 o 3234r1 2 /tod i/o a 7 i 10 12 reset i v cc 33 35 r1 3 / evnb i/o a 8 i 11 13 x1 i gnd 34 36 r2 0 /evnd i/o a 0 i 12 14 x2 o 35 37 r2 1 / sck i/o a 10 i 13 15 gnd gnd 36 38 r2 2 /si i/o a 11 i 14 16 d 0 i/o ce i3739r2 3 /so i/o a 12 i 15 17 d 1 i/o oe i3840r3 0 /seg1 i/o a 13 i 16 18 d 2 i/o v cc 39 41 r3 1 /seg2 i/o a 14 i 17 19 d 3 i/o v cc 40 42 r3 2 /seg3 i/o o 0 i/o 18 20 d 4 i/o 41 43 r3 3 /seg4 i/o o 1 i/o 19 21 d 5 i/o 42 44 r4 0 /seg5 i/o o 2 i/o 20 22 d 6 i/o 43 45 r4 1 /seg6 i/o o 3 i/o 21 23 d 7 i/o 44 46 r4 2 /seg7 i/o o 4 i/o 22 24 d 8 i/o 45 47 r4 3 /seg8 i/o o 5 i/o 23 25 d 9 i/o 46 48 r5 0 /seg9 i/o o 6 i/o notes on next page.
hd404629r series 115 prom mode pin description (cont) pin no. mcu mode prom mode pin no. mcu mode prom mode fp-100b tfp-100b fp-100a pin name i/o pin name i/o fp-100b tfp-100b fp-100a pin name i/o pin name i/o 47 49 r5 1 /seg10 i/o o 7 i/o 74 76 seg37 o 48 50 r5 2 /seg11 i/o o 4 i/o 75 77 seg38 o 49 51 r5 3 /seg12 i/o o 3 i/o 76 78 seg39 o 50 52 r6 0 /seg13 i/o o 2 i/o 77 79 seg40 o 51 53 r6 1 /seg14 i/o o 1 i/o 78 80 seg41 o 52 54 r6 2 /seg15 i/o o 0 i/o 79 81 seg42 o 53 55 r6 3 /seg16 i/o v cc 80 82 seg43 o 54 56 r7 0 /seg17 i/o a 1 i 81 83 seg44 o 55 57 r7 1 /seg18 i/o a 2 i 82 84 seg45 o 56 58 r7 2 /seg19 i/o a 3 i 83 85 seg46 o 57 59 r7 3 /seg20 i/o a 4 i 84 86 seg47 o 58 60 seg21 o 85 87 seg48 o 59 61 seg22 o 86 88 seg49 o 60 62 seg23 o 87 89 seg50 o 61 63 seg24 o 88 90 seg51 o 62 64 seg25 o 89 91 seg52 o 63 65 seg26 o 90 92 com1 o 64 66 seg27 o 91 93 com2 o 65 67 seg28 o 92 94 com3 o 66 68 seg29 o 93 95 com4 o 67 69 seg30 o 94 96 v 1 68 70 seg31 o 95 97 v 2 69 71 seg32 o 96 98 v 3 70 72 seg33 o 97 99 v cc v cc 71 73 seg34 o 98 100 tonec o 72 74 seg35 o 99 1 toner o 73 75 seg36 o 100 2 vt ref notes: 1. i/o: input/output pin, i: input pin, o: output pin 2. each of o 0 ? 4 has two pins; before using, each pair must be connected together.
hd404629r series 116 prom mode pin functions v pp : applies the programming voltage (12.5 v 0.3 v) to the built-in prom. ce : inputs a control signal to enable prom programming and verification. oe : inputs a data output control signal for verification. a 0 ? 14 : act as address input pins of the built-in prom. o 0 ? 7 : act as data bus input pins of the built-in prom. each of o 0 ? 4 has two pins; before using these pins, connect each pair together. m 0 , m 1 , reset, test : used to set prom mode. the mcu is set to the prom mode by pulling m 0 , m 1 , and test low, and reset high. other pins (fp-100b/fp-100a): connect pins 1/3 (av cc ), 8/10 (osc 1 ), 16/18 (d 2 ), 17/19 (d 3 ), 53/55 (r6 3 /seg16), and 97/99 (v cc ) to v cc , and pins 6/8 (av ss ) and 11/13 (x1) to gnd. leave other pins open. $0000 vector address zero-page subroutine (64 words) pattern (4,096 words) program (16,384 words) $0001 $001f $0080 $007f $2000 $1fff $0020 $7fff bit 4 bit 8 bit 3 bit 7 bit 2 bit 6 bit 1 bit 5 bit 0 bit 9 upper three bits are not to be used (fill them with 111) upper 5 bits lower 5 bits $0000 $000f $0010 $003f $0040 $3fff $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000a $000b $000c $000d $000e $000f jmpl instruction (jump to reset, stopc routine) jmpl instruction (jump to int 0 routine) jmpl instruction (jump to timer a routine) jmpl instruction (jump to timer b, int 2 routine) jmpl instruction (jump to int 1 routine) jmpl instruction (jump to timer c, int 3 routine) jmpl instruction (jump to timer d, int 4 routine) . . . . . . . . . jmpl instruction (jump to a/d, serial routine) $0fff $1000 11 1 11 1 figure 102 memory map in prom mode
hd404629r series 117 start verification ok? set programming/verification modes v = 12.5 0.3 v, v = 6.0 0.25 v pp cc address = 0 n = 0 n + 1 n ? program t =1 ms 5% pw program t = 3n ms opw last address? n < 25? yes no no no address + 1 address ? yes set read mode v = 5.0 0.5 v, v = v 0.6 v cc pp cc all addresses read? end fail no yes yes figure 103 flowchart of high-speed programming
hd404629r series 118 programming electrical characteristics dc characteristics (v cc = 6.0 v 0.25 v, v pp = 12.5 v 0.3 v, t a = 25 c 5 c, unless otherwise specified) item symbol pin(s) min typ max unit test condition input high v ih o 0 ? 7 , a 0 ? 14 , 2.2 v cc + 0.3 v voltage level oe , ce input low v il o 0 ? 7 , a 0 ? 14 , ?.3 0.8 v voltage level oe , ce output high v oh o 0 ? 7 2.4 v i oh = ?00 m a voltage level output low v ol o 0 ? 7 0.4 v i ol = 1.6 ma voltage level input leakage ? i il ? o 0 ? 7 , a 0 ? 14 , 2 m av in = 5.25 v/0.5 v current oe , ce v cc current i cc 30 ma v pp current i pp 40 ma ac characteristics (v cc = 6.0 v 0.25 v, v pp = 12.5 v 0.3 v, t a = 25 c 5 c, unless otherwise specified) item symbol min typ max unit test condition address setup time t as 2 m s see figure 108 oe setup time t oes 2 m s data setup time t ds 2 m s address hold time t ah 0 m s data hold time t dh 2 m s data output disable time t df 130 ns v pp setup time t vps 2 m s program pulse width t pw 0.95 1.0 1.05 ms ce pulse width during t opw 2.85 78.75 ms overprogramming v cc setup time t vcs 2 m s data output delay time t oe 0 500 ns
hd404629r series 119 address data data in stable data out valid v pp v pp v cc gnd gnd v cc ce oe t as t ds t vps t vcs t dh t pw t opw t oes t oe t ah t df programming verification input pulse level: 0.8 v to 2.2 v input rise/fall time: 20 ns input timing reference levels: 1.0 v, 2.0 v output timing reference levels: 0.8 v, 2.0 v figure 104 prom programming/verification timing
hd404629r series 120 notes on prom programming principles of programming/erasure: a memory cell in a ztat microcomputer is the same as an eprom cell; it is programmed by applying a high voltage between its control gate and drain to inject hot electrons into its floating gate. these electrons are stable, surrounded by an energy barrier formed by an sio 2 film. the change in threshold voltage of a memory cell with a charged floating gate makes the corresponding bit appear as 0; a cell whose floating gate is not charged appears as a 1 bit (figure 105). the charge in a memory cell may decrease with time. this decrease is usually due to one of the following causes: ? ultraviolet light excites electrons, allowing them to escape. this effect is the basis of the erasure principle. ? heat excites trapped electrons, allowing them to escape. ? high voltages between the control gate and drain may erase electrons. if the oxide film covering a floating gate is defective, the electron erasure rate will be greater. however, electron erasure does not often occur because defective devices are detected and removed at the testing stage. control gate floating gate drain sio 2 source nn ++ control gate floating gate drain sio 2 source nn ++ erasure (1) write (0) figure 105 cross-sections of a prom cell prom programming: prom memory cells must be programmed under specific voltage and timing conditions. the higher the programming voltage v pp and the longer the programming pulse t pw is applied, the more electrons are injected into the floating gates. however, if v pp exceeds specifications, the pn junctions may be permanently damaged. pay particular attention to overshooting in the prom programmer. in addition, note that negative voltage noise will produce a parasitic transistor effect that may reduce breakdown voltages. the ztat microcomputer is electrically connected to the prom programmer by a socket adapter. therefore, note the following points: ? check that the socket adapter is firmly mounted on the prom programmer. ? do not touch the socket adapter or the lsi during the programming. touching them may affect the quality of the contacts, which will cause programming errors.
hd404629r series 121 prom reliability after programming: in general, semiconductor devices retain their reliability, provided that some initial defects can be excluded. these initial defects can be detected and rejected by screening. baking devices under high-temperature conditions is one method of screening that can rapidly eliminate data-hold defects in memory cells. (refer to the previous principles of programming/erasure section.) ztat microcomputer devices are extremely reliable because they have been subjected to such a screening method during the wafer fabrication process, but hitachi recommends that each device be exposed to 150 c at one atmosphere for at least 48 hours after it is programmed, to ensure its best performance. the recommended screening procedure is shown in figure 106. note: if programming errors occur continuously during prom programming, suspend programming and check for problems in the prom programmer or socket adapter. if programming verification indicates errors in programming or after high-temperature exposure, please inform hitachi. note: exposure time is measured from when the temperature in the heater reaches 150?. programming, verification exposure to high temperature, without power 150? ?10?, 48 h +8 h 0 h * * program read check v = 4.5 v or 5.5 v cc figure 106 recommended screening procedure
hd404629r series 122 addressing modes ram addressing modes the mcu has three ram addressing modes, as shown in figure 107 and described below. register indirect addressing mode: the contents of the w, x, and y registers (10 bits in total) are used as a ram address. direct addressing mode: a direct addressing instruction consists of two words. the first word contains the opcode, and the contents of the second word (10 bits) are used as a ram address. memory register addressing mode: the memory registers (mr), which are located in 16 addresses from $040 to $04f, are accessed with the lamr and xmra instructions. ap 9 ap 0 w 1 y 0 w register x register y register ram address register direct addressing ap 9 ap 0 ram address direct addressing d 9 d 0 2nd word of instruction opcode 1st word of instruction ap 9 ap 0 ram address memory register addressing m 3 opcode instruction 000100 ap 8 ap 7 ap ap 5 ap 4 6 ap 3 ap 2 ap 1 ap ap ap ap ap ap ap ap 87654321 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 ap 8 ap 7 ap 6 ap 5 ap 4 ap 3 ap 2 ap 1 w 0 x 3 x 2 x 1 x 0 y 3 y 2 y 1 m 2 m 1 m 0 figure 107 ram addressing modes
hd404629r series 123 rom addressing modes and the p instruction the mcu has four rom addressing modes, as shown in figure 108 and described below. direct addressing mode: a program can branch to any address in the rom memory space by executing the jmpl, brl, or call instruction. each of these instructions replaces the 14 program counter bits (pc 13 ?c 0 ) with 14-bit immediate data. current page addressing mode: the mcu has 64 pages of rom with 256 words per page. a program can branch to any address in the current page by executing the br instruction. this instruction replaces the eight low-order bits of the program counter (pc 7 ?c 0 ) with eight-bit immediate data. if the br instruction is on a page boundary (address 256n + 255), executing that instruction transfers the pc contents to the next physical page, as shown in figure 105. this means that the execution of the br instruction on a page boundary will make the program branch to the next page. note that the hmcs400-series cross macroassembler has an automatic paging feature for rom pages. zero-page addressing mode: a program can branch to the zero-page subroutine area located at $0000 $003f by executing the cal instruction. when the cal instruction is executed, 6 bits of immediate data are placed in the six low-order bits of the program counter (pc 5 ?c 0 ), and 0s are placed in the eight high- order bits (pc 13 ?c 6 ). table data addressing mode: a program can branch to an address determined by the contents of four-bit immediate data, the accumulator, and the b register by executing the tbr instruction. p instruction: rom data addressed in table data addressing mode can be referenced with the p instruction as shown in figure 109. if bit 8 of the rom data is 1, eight bits of rom data are written to the accumulator and the b register. if bit 9 is 1, eight bits of rom data are written to the r1 and r2 port output registers. if both bits 8 and 9 are 1, rom data is written to the accumulator and the b register, and also to the r1 and r2 port output registers at the same time. the p instruction has no effect on the program counter.
hd404629r series 124 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 2nd word of instruction opcode 1st word of instruction [jmpl] [brl] [call] pc 9 pc 8 pc 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc 0 pcpcpcpc 10111213 program counter direct addressing zero page addressing d 5 d 4 d 3 d 2 d 1 d 0 instruction [cal] opcode pc 98 pc 76 pc 54 pc 3 pc 1 pc 0 pc pc 10111213 program counter 00 00 0000 pc pc pc pc pc pc 2 b 1 b 0 a 3 a 2 a 1 a 0 accumulator program counter table data addressing pc 9 pc 8 pc 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc 0 pcpcpc 10111213 b 2 b 3 b register p 3 p 0 [tbr] instruction opcode 00 p 2 p 1 pc opcode b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 instruction pc 90 pcpcpc 111213 program counter current page addressing [br] pc 10 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc pc 8 pc p 0 p 1 p 2 p 3 figure 108 rom addressing modes
hd404629r series 125 b 1 b 0 a 3 a 2 a 1 a 0 accumulator referenced rom address address designation ra 9 ra 8 ra 7 ra 6 ra 5 ra 4 ra 3 ra 2 ra 1 ra 0 rarara 10 11 12 13 b 2 b 3 b register 00 p 3 p 0 [p] instruction opcode p 2 p 1 ra ro 9 ro 0 ro 8 ro 7 ro 6 ro 5 ro 4 ro 3 ro 2 ro 1 bbbb aa a a 3210 3210 if ro = 1 8 accumulator, b register rom data pattern output ro 9 rom data r2 3 if ro = 1 9 output registers r1, r2 r2 2 r2 1 r2 0 r1 3 r1 2 r1 1 r1 0 ro 0 ro 8 ro 7 ro 6 ro 5 ro 4 ro 3 ro 2 ro 1 figure 109 p instruction
hd404629r series 126 br aaa aaa nop 256 (n ?1) + 255 256n br aaa br bbb 256n + 254 256n + 255 256 (n + 1) bbb nop figure 110 branching when the branch destination is on a page boundary
hd404629r series 127 instruction set the mcu has 101 instructions, classified into the following 10 groups: immediate instructions register-to-register instructions ram addressing instructions ram register instructions arithmetic instructions compare instructions ram bit manipulation instructions rom addressing instructions input/output instructions control instructions the functions of these instructions are listed in tables 34 to 43, and an opcode map is shown in table 44. table 34 immediate instructions words/ operation mnemonic operation code function status cycles load a from lai i 100011 i 3 i 2 i 1 i 0 i ? a 1/1 immediate load b from lbi i 100000 i 3 i 2 i 1 i 0 i ? b 1/1 immediate load memory lmid i,d 011010 i 3 i 2 i 1 i 0 i ? m 2/2 from d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 immediate load memory lmiiy i 101001 i 3 i 2 i 1 i 0 i ? m, nz 1/1 from immediate, y + 1 ? y increment y
hd404629r series 128 table 35 register-register instructions words/ operation mnemonic operation code function status cycles load a lab 000100 1000 b ? a 1/1 from b load b lba 001100 1000 a ? b 1/1 from a load a law * 010000 0000 w ? a 2/2 * from w 000000 0000 load a lay 001010 1111 y ? a 1/1 from y load a laspx 000110 1000 spx ? a 1/1 from spx load a laspy 000101 1000 spy ? a 1/1 from spy load a lamr m 100111 m 3 m 2 m 1 m 0 mr (m) ? a 1/1 from mr exchange xmra m 101111 m 3 m 2 m 1 m 0 mr (m) ? a 1/1 mr and a note: * although the law and lwa instructions require an operand ($000) in the second word, the assembler generates it automatically and thus there is no need to specify it explicitly.
hd404629r series 129 table 36 ram address instructions words/ operation mnemonic operation code function status cycles load w from lwi i 001111 00i 1 i 0 i ? w 1/1 immediate load x from lxi i 100010 i 3 i 2 i 1 i 0 i ? x 1/1 immediate load y from lyi i 100001 i 3 i 2 i 1 i 0 i ? y 1/1 immediate load w lwa 010001 0000 a ? w 2/2 * from a 000000 0000 load x lxa 001110 1000 a ? x 1/1 from a load y lya 001101 1000 a ? y 1/1 from a increment y iy 000101 1100 y + 1 ? y nz 1/1 decrement y dy 001101 1111 y 1 ? y nb 1/1 add a to y ayy 000101 0100 y + a ? y ovf 1/1 subtract a syy 001101 0100 y a ? y nb 1/1 from y exchange x xspx 000000 0001 x ? spx 1/1 and spx exchange y xspy 000000 0010 y ? spy 1/1 and spy exchange x xspxy 000000 0011 x ? spx, 1/1 and spx, y ? spy y and spy note: * although the law and lwa instructions require an operand ($000) in the second word, the assembler generates it automatically and thus there is no need to specify it explicitly.
hd404629r series 130 table 37 ram register instructions operation mnemonic operation code function status words/ cycles load a from memory lam 001001 0000 m ? a 1/1 lamx 001001 0001 m ? a, x ? spx lamy 001001 0010 m ? a, y ? spy lamxy 001001 0011 m ? a, x ? spx, y ? spy load a from memory lamd d 0 d 9 1 d 8 1 d 7 0 d 6 0 d 5 1 d 4 0 d 3 0 d 2 0 d 1 0 d 0 m ? a 2/2 load b from memory lbm 000100 0000 m ? b 1/1 lbmx 000100 0001 m ? b, x ? spx lbmy 000100 0010 m ? b, y ? spy lbmxy 000100 0011 m ? b, x ? spx, y ? spy load memory from a lma 001001 0100 a ? m 1/1 lmax 001001 0101 a ? m, x ? spx lmay 001001 0110 a ? m, y ? spy lmaxy 001001 0111 a ? m, x ? spx, y ? spy load memory from a lmad d 0 d 9 1 d 8 1 d 7 0 d 6 0 d 5 1 d 4 0 d 3 0 d 2 0 d 1 0 d 0 a ? m 2/2
hd404629r series 131 table 37 ram register instructions (cont) operation mnemonic operation code function status words/ cycles load memory from a, increment y lmaiy 000101 0000 a ? m, y + 1 ? y nz 1/1 lmaiyx 000101 0001 a ? m, y + 1 ? y, x ? spx load memory from a, decrement y lmady 001101 0000 a ? m, y ?1 ? y nb 1/1 lmadyx 001101 0001 a ? m, y ?1 ? y, x ? spx exchange memory and a xma 001000 0000 m ? a 1/1 xmax 001000 0001 m ? a, x ? spx xmay 001000 0010 m ? a, y ? spy xmaxy 001000 0011 m ? a, x ? spx, y ? spy exchange memory and a xmad d 0 d 9 1 d 8 1 d 7 0 d 6 0 d 5 0 d 4 0 d 3 0 d 2 0 d 1 0 d 0 m ? a 2/2 exchange memory and b xmb 001100 0000 m ? b 1/1 xmbx 001100 0001 m ? b, x ? spx xmby 001100 0010 m ? b, y ? spy xmbxy 001100 0011 m ? b, x ? spx, y ? spy
hd404629r series 132 table 38 arithmetic instructions words/ operation mnemonic operation code function status cycles add immediate to ai i 101000 i 3 i 2 i 1 i 0 a + i ? a ovf 1/1 a increment b ib 000100 1100 b + 1 ? b nz 1/1 decrement b db 001100 1111 b 1 ? b nb 1/1 decimal daa 001010 0110 1/1 adjust for addition decimal das 001010 1010 1/1 adjust for subtraction negate a nega 000110 0000 a + 1 ? a 1/1 complement comb 010100 0000 b ? b 1/1 b rotate right a rotr 001010 0000 1/1 with carry rotate left a rotl 001010 0001 1/1 with carry set carry sec 001110 1111 1 ? ca 1/1 reset carry rec 001110 1100 0 ? ca 1/1 test carry tc 000110 1111 ca 1/1 add a to memory am 000000 1000 m + a ? a ovf 1/1 add a to memory amd d 010000 1000 m + a ? a ovf 2/2 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 add a to memory amc 000001 1000 m + a + ca ? a ovf 1/1 with carry ovf ? ca add a to memory amcd d 010001 1000 m + a + ca ? a ovf 2/2 with carry d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 ovf ? ca subtract a smc 001001 1000 m a ca ? a nb 1/1 from memory nb ? ca with carry subtract a smcd d 011001 1000 m a ca ? a nb 2/2 from memory d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 nb ? ca with carry or a and b or 010100 0100 a b ? a 1/1
hd404629r series 133 table 38 arithmetic instructions (cont) words/ operation mnemonic operation code function status cycles and memory anm 001001 1100 a ? m ? a nz 1/1 with a and memory anmd d 011001 1100 a ? m ? a nz 2/2 with a d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 or memory orm 000000 1100 a m ? a nz 1/1 with a or memory ormd d 010000 1100 a m ? a nz 2/2 with a d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 eor memory eorm 000001 1100 a ? m ? a nz 1/1 with a eor memory eormd d 010001 1100 a ? m ? a nz 2/2 with a d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0
hd404629r series 134 table 39 compare instructions words/ operation mnemonic operation code function status cycles immediate not inem i 000010 i 3 i 2 i 1 i 0 i 1 m nz 1/1 equal to memory immediate not inemd i, d 010010 i 3 i 2 i 1 i 0 i 1 m nz 2/2 equal to d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 memory a not equal to anem 000000 0100 a 1 m nz 1/1 memory a not equal to anemd d 010000 0100 a 1 m nz 2/2 memory d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 b not equal to bnem 000100 0100 b 1 m nz 1/1 memory y not equal to ynei i 000111 i 3 i 2 i 1 i 0 y 1 i nz 1/1 immediate immediate ilem i 000011 i 3 i 2 i 1 i 0 i m nb 1/1 less or equal to memory immediate ilemd i, d 010011 i 3 i 2 i 1 i 0 i m nb 2/2 less or equal d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 to memory a less or alem 000001 0100 a m nb 1/1 equal to memory a less or alemd d 010001 0100 a m nb 2/2 equal to d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 memory b less or blem 001100 0100 b m nb 1/1 equal to memory a less or alei i 101011 i 3 i 2 i 1 i 0 a i nb 1/1 equal to immediate
hd404629r series 135 table 40 ram bit manipulation instructions words/ operation mnemonic operation code function status cycles set memory bit sem n 001000 01n 1 n 0 i ? m (n) 1/1 set memory bit semd n,d 011000 01n 1 n 0 i ? m (n) 2/2 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 reset memory rem n 001000 10n 1 n 0 0 ? m (n) 1/1 bit reset memory remd n,d 011000 10n 1 n 0 0 ? m (n) 2/2 bit d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 test memory bit tm n 001000 11n 1 n 0 m (n) 1/1 test memory bit tm n,d 011000 11n 1 n 0 m (n) 2/2 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 table 41 rom addressing instructions words/ operation mnemonic operation code function status cycles branch on br b 1 1 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 1 1/1 status 1 long branch brl u 01011 1p 3 p 2 p 1 p 0 1 2/2 on status 1 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 long jump jmpl u 01010 1p 3 p 2 p 1 p 0 2/2 unconditionally d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 subroutine jump cal a 0111a 5 a 4 a 3 a 2 a 1 a 0 1 1/2 on status 1 long subroutine call u 01011 0p 3 p 2 p 1 p 0 1 2/2 jump on status 1 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 table branch tbr p 00101 1p 3 p 2 p 1 p 0 1 1/1 return from rtn 00000 10000 1/3 subroutine return from rtni 00000 10001 1 ? ie, st 1/3 interrupt carry restored
hd404629r series 136 table 42 input/output instructions words/ operation mnemonic operation code function status cycles set discrete sed 00111 00100 1 ? d (y) 1/1 i/o latch set discrete sedd m 10111 0m 3 m 2 m 1 m 0 1 ? d (m) 1/1 i/o latch direct reset red 00011 00100 0 ? d (y) 1/1 discrete i/o latch reset redd m 10011 0m 3 m 2 m 1 m 0 0 ? d (m) 1/1 discrete i/o latch direct test discrete i/o td 00111 00000 d (y) 1/1 latch test discrete i/o tdd m 10101 0m 3 m 2 m 1 m 0 d (m) 1/1 latch direct load a lar m 10010 1m 3 m 2 m 1 m 0 r (m) ? a 1/1 from r-port register load b lbr m 10010 0m 3 m 2 m 1 m 0 r (m) ? b 1/1 from r-port register load r-port lra m 10110 1m 3 m 2 m 1 m 0 a ? r (m) 1/1 register from a load r-port lrb m 10110 0m 3 m 2 m 1 m 0 b ? r (m) 1/1 register from b pattern p p 01101 1p 3 p 2 p 1 p 0 1/2 generation
hd404629r series 137 table 40 control instructions words/ operation mnemonic operation code function status cycles no operation nop 00000 00000 1/1 start serial sts 01010 01000 1/1 standby sby 01010 01100 1/1 mode/watch mode * stop mode/ stop 01010 01101 1/1 watch mode note: * only on return from subactive mode.
hd404629r series 138 table 44 opcode map r8 l h r9 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 1 2 3 4 5 6 7 8 9 a b c d e f lbi i(4) lyi i(4) lxi i(4) lai i(4) lbr m(4) lar m(4) redd m(4) lamr m(4) ai i(4) lmiiy i(4) tdd m(4) alei i(4) lrb m(4) lra m(4) sedd m(4) xmra m(4) 0 0 1 1-word/2-cycle instruction 1-word/3-cycle instruction ram direct address instruction (2-word/2-cycle) 2-word/2-cycle instruction 0123456789abcdef nop xspx xspy xspxy anem am orm lbm(xy) bnem lab ib lmaiy(x) ayy laspy iy rtn rtni alem amc eorm nega red laspx tc inem i(4) ilem i(4) ynei i(4) xma(xy) lam(xy) sem n(2) lma(xy) rem n(2) smc tm n(2) anm rotr daa das lay rotl db dy sec lba lya rec lxa blem syy sed xmb(xy) lmady(x) td lwi i(2) tbr p(4)
hd404629r series 139 table 44 opcode map (cont) r8 l h r9 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 1 2 3 4 5 6 7 8 9 a b c d e f 1 0 1 1-word/2-cycle instruction 1-word/3-cycle instruction ram direct address instruction (2-word/2-cycle) 2-word/2-cycle instruction 0123456789abcdef law anemd amd ormd lwa alemd amcd eormd comb or sts sby stop inemd i(4) ilemd i(4) jmpl p(4) call p(4) brl p(4) xmad lamd semd n(2) lmad remd n(2) smcd tmd n(2) anmd lmid i(4) cal a(6) br b(8) p p(4)
hd404629r series 140 absolute maximum ratings item symbol value unit notes supply voltage v cc ?.3 to +7.0 v programming voltage v pp ?.3 to +14.0 v 1 pin voltage v t ?.3 to (v cc + 0.3) v total permissible input current ? i o 100 ma 2 total permissible output current ? i o 50 ma 3 maximum input current i o 4 ma 4, 5 30 ma 4, 6 maximum output current ? o 4 ma 7, 8 operating temperature t opr ?0 to +75 c storage temperature t stg ?5 to +125 c notes: permanent damage may occur if these absolute maximum ratings are exceeded. normal operation must be under the conditions stated in the electrical characteristics tables. if these conditions are exceeded, the lsi may malfunction or its reliability may be affected. 1. applies to d 11 (v pp ) of the hd4074629. 2. the total permissible input current is the total of input currents simultaneously flowing in from all the i/o pins to ground. 3. the total permissible output current is the total of output currents simultaneously flowing out from v cc to all i/o pins. 4. the maximum input current is the maximum current flowing from each i/o pin to ground. 5. applies to r0?7. 6. applies to d 0 ? 9 . 7. the maximum output current is the maximum current flowing out from v cc to each i/o pin. 8. applies to d 0 ? 9 and r0?7.
hd404629r series 141 electrical characteristics dc characteristics (hd404628r, hd4046212r, hd404629r: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = ?0 c to +75 c; hd4074629: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 c to +75 c, unless otherwise specified) item symbol pin(s) min typ max unit test condition notes input high voltage v ih reset, sck , si, int 0 , int 1 int 2 , int 3 , int 4 , stopc , evnb , evnd 0.9v cc ? cc + 0.3 v osc 1 v cc ?0.3 v cc + 0.3 v external clock operation input low voltage v il reset, sck , si, int 0 , int 1 , int 2 , int 3 , int 4 , stopc, evnb , evnd ?.3 0.1v cc v osc 1 ?.3 0.3 v external clock operation output high voltage v oh sck, so, tob, toc, tod v cc ?1.0 v ? oh = 0.5 ma output low voltage v ol sck, so, tob, toc, tod 0.4 v i ol = 0.4 ma i/o leakage current ? i i l ? reset, sck , si, int 0 , int 1 , int 2 , int 3 , int 4 , stopc, evnb , evnd, osc 1 , tob, toc, tod, so 1.0 m a v in = 0 v to v cc 1 current dissipation in active mode i cc1 v cc (hd404628r, hd4046212r, hd404629r) 2.5 5.0 ma v cc = 5.0 v, f osc = 4 mhz 2, 4 v cc (hd4074629) ?9 i cc2 v cc (hd404628r, hd4046212r, hd404629r) 0.3 0.9 ma v cc = 3.0 v, f osc = 800 khz 2, 4 v cc (hd4074629) 0.6 1.8 current dissipation in standby mode i sby1 v cc (hd404628r, hd4046212r, hd404629r) 1.0 2.0 ma v cc = 5.0 v, f osc = 4 mhz, lcd on 3, 4 v cc (hd4074629) 1.2 3 i sby2 v cc 0.2 0.7 ma v cc = 3.0 v, f osc = 800 khz, lcd on 3, 4 notes on next page.
hd404629r series 142 dc characteristics (hd404628r, hd4046212r, hd404629r: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = ?0 c to +75 c; hd4074629: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 c to +75 c, unless otherwise specified) (cont) item symbol pin(s) min typ max unit test condition notes current dissipation in subactive mode i sub v cc ?570 m a hd404628r, hd4046212r, hd404629r: v cc = 3.0 v, lcd on 32-khz oscillator 4 70 150 m a hd4074629: v cc = 3.0 v, lcd on 32-khz oscillator 4 current dissipation in i wtc1 v cc (hd404628r, hd4046212r, hd404629r) ?540 m av cc = 3.0 v, lcd on 32-khz oscillator 4 v cc (hd4074629) ?840 watch mode i wtc2 v cc (hd404628r, hd4046212r, hd404629r) ?10 m av cc = 3.0 v, lcd off 32-khz oscillator 4 v cc (hd4074629) ?15 current dissipation in stop mode i stop v cc (hd404628r, hd4046212r, hd404629r) 0.5 5 m av cc = 3.0 v, no 32-khz oscillator 4 v cc (hd4074629) ?10 stop mode retaining voltage v stop v cc 2 v no 32-khz oscillator 5 notes: 1. output buffer current is excluded. 2. i cc1 and i cc2 are the source currents when no i/o current is flowing while the mcu is in reset state. test conditions: mcu: reset pins: reset at v cc (v cc ?0.3 v to v cc ) test at v cc (v cc ?0.3 v to v cc ) 3. i sby1 and i sby2 are the source currents when no i/o current is flowing while the mcu timer is operating. test conditions: mcu: i/o reset serial interface stopped dtmf stopped standby mode pins: reset at gnd (0 v to 0.3 v) test at v cc (v cc ?0.3 v to v cc ) 4. these are the source currents when no i/o current is flowing. test conditions: pins: reset at gnd (0 v to 0.3 v) test at v cc (v cc ?0.3 v to v cc ) d 11 (v pp ) at v cc (v cc ?0.3 v to v cc ) for the hd4074629 5. the required voltage for ram data retention.
hd404629r series 143 i/o characteristics for standard pins (hd404628r, hd4046212r, hd404629r: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = ?0 c to +75 c; hd4074629: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 c to +75 c, unless otherwise specified) item symbol pin(s) min typ max unit test condition notes input high voltage v ih d 10 , d 11 , r0?7 0.7v cc ? cc + 0.3 v input low voltage v il d 10 , d 11 , r0?7 ?.3 0.3v cc v output high voltage v oh r0?7 v cc ?1.0 v ? oh = 0.5 ma output low voltage v ol r0?7 0.4 v i ol = 0.4 ma i/o leakage ? i i l ? d 10 , r0?7 1 m av in = 0 v to v cc 1 current d 11 1 m a hd404628r, hd4046212r, hd404629r: v in = 0 v to v cc 1 1 m a hd4074629: v in = v cc ?0.3 v to v cc 1 20 m a hd4074629: v in = 0 v to 0.3 v 1 pull-up mos current ? pu r0?7 5 30 90 m av cc = 3.0 v, v in = 0 v note: 1. output buffer current is excluded.
hd404629r series 144 i/o characteristics for high-current pins (hd404628r, hd4046212r, hd404629r: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = ?0 c to +75 c; hd4074629: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 c to +75 c, unless otherwise specified) item symbol pin(s) min typ max unit test condition notes input high voltage v ih d 0 ? 9 0.7v cc ? cc + 0.3 v input low voltage v il d 0 ? 9 ?.3 0.3v cc v output high voltage v oh d 0 ? 9 v cc ?1.0 v ? oh = 0.5 ma output low v ol d 0 ? 9 0.4 v i ol = 0.4 ma voltage 2.0 v i ol = 15 ma, v cc = 4.5 v to 6.0 v 1 i/o leakage current ? i i l ? d 0 ? 9 1 m av in = 0 v to v cc 2 pull-up mos current ? pu d 0 ? 9 53 09 0 m av cc = 3 v, v in = 0 v note: 1. the test condition of hd4074629 is v cc = 4.5 v to 5.5 v. 2. output buffer current is excluded. lcd circuit characteristics (hd404628r, hd4046212r, hd404629r: v cc = 2.7 to 6.0 v, gnd = 0 v, t a ? ?0 c to +75 c; hd4074629: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 c to +75 c, unless otherwise specified) item symbol pin(s) min typ max unit test condition notes segment driver voltage drop v ds seg1?eg52 0.6 v i pd = 3 m a1 common driver voltage drop v dc com1?om4 0.3 v i pd = 3 m a1 lcd power supply division resistance r w (hd404628r, hd4046212r, hd404629r) 50 300 900 k w between v 1 and gnd (hd4074629) 100 300 900 lcd voltage v lcd v 1 2.7 v cc v 2 notes: 1. v ds and v dc are the voltage drops from power supply pins v 1 , v 2 , v 3 , and gnd to each segment pin and each common pin, respectively. 2. when v lcd is supplied from an external source, the following relations must be retained: v cc 3 v 1 3 v 2 3 v 3 3 gnd
hd404629r series 145 dtmf characteristics (hd404628r, hd4046212r, hd404629r: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = ?0 c to +75 c; hd4074629: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 c to +75 c, unless otherwise specified) item symbol pin min typ max unit test condition notes tone output voltage (1) v or toner 500 660 mv rms vt ref ?gnd = 2.0 v, r l = 100 k w 1 tone output voltage (2) v oc tonec 520 690 mv rms vt ref ?gnd = 2.0 v, r l = 100 k w 1 tone output distortion % dis 3 7 % short circuit between toner and tonec, r l = 100 k w 2 tone output ratio db cr 2.5 db short circuit between toner and tonec, r l = 100 k w 2 notes: 1. see figure 106. 2. see figure 107. 3. 400 khz, 800 khz, 2 mhz, or 4 mhz can be used as the operating frequency (f osc ).
hd404629r series 146 a/d converter characteristics (hd404628r, hd4046212r, hd404629r: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = ?0 c to +75 c; hd4074629: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 c to +75 c, unless otherwise specified) item symbol pin(s) min typ max unit test condition notes analog power voltage av cc av cc v cc ?0.3 v cc v cc + 0.3 v av cc 3 2.7 v analog input voltage av in an 0 ?n 3 av ss ?v cc v current between av cc and av ss i a d (hd404628r, hd4046212r, hd404629r) 250 m av cc = av cc = 5.0 v (hd4074629) 50 150 analog input capacitance ca in an 0 ?n 3 15 pf resolution 8 8 8 bit number of inputs 0 4 chan- nel absolute accuracy 2.0 lsb t a = 25 c, v cc = 4.5?.5 v conversion time 34 67 t cyc input impedance an 0 ?n 3 1m w f osc = 1 mhz, v in = 0.0 v
hd404629r series 147 ac characteristics (hd404628r, hd4046212r, hd404629r: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = ?0 c to +75 c; hd4074629: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 c to +75 c, unless otherwise specified) item symbol pin(s) min typ max unit test condition notes clock oscillation f osc osc 1 , osc 2 400 khz 1/4 division 1 frequency 800 khz 1/4 division 1 2 mhz 1/4 division 1 4 mhz 1/4 division; hd404628, hd4046212, hd404629: v cc = 3.0 to 6.0 v 1 x1, x2 32.768 khz instruction cycle t cyc 10 m sf osc = 400 khz time 5 m sf osc = 800 khz ? m sf osc = 2 mhz ? m sf osc = 4 mhz; hd404628, hd4046212, hd404629: v cc = 3.0 to 6.0 v t subcyc 244.14 m s 32-khz oscillator, 1/8 division 122.07 m s 32-khz oscillator, 1/4 division oscillation t rc osc 1 , osc 2 7.5 ms ceramic oscillator 2 stabilization time osc 1 , osc 2 (hd404628r, hd4046212r, hd404629r) 30 ms crystal oscillator v cc = 3.0 to 6.0 v 2 x1, x2 3 s t a = ?0 c to +60 c 3 external clock t cph osc 1 1100 ns f osc = 400 khz 4 high width 550 ns f osc = 800 khz 4 215 ns f osc = 2 mhz 4 105 ns f osc = 4 mhz 4 external clock t cpl osc 1 1100 ns f osc = 400 khz 4 low width 550 ns f osc = 800 khz 4 215 ns f osc = 2 mhz 4 105 ns f osc = 4 mhz 4 external clock t cpr osc 1 150 ns f osc = 400 khz 4 rise time 75 ns f osc = 800 khz 4 35 ns f osc = 2 mhz 4 20 ns f osc = 4 mhz 4 notes on next page.
hd404629r series 148 ac characteristics (hd404628r, hd4046212r, hd404629r: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = ?0 c to +75 c; hd4074629: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 c to +75 c, unless otherwise specified) (cont) item symbol pin(s) min typ max unit test condition notes external clock t cpf osc 1 150 ns f osc = 400 khz 4 fall time 75 ns f osc = 800 khz 4 35 ns f osc = 2 mhz 4 20 ns f osc = 4 mhz 4 int 0 ?nt 4 , evnb , evnd high widths t i h int 0 ?nt 4 , evnb , evnd 2 t cyc / t subcyc ? int 0 ?nt 4 , evnb , evnd low widths t i l int 0 ?nt 4 , evnb , evnd 2 t cyc / t subcyc ? reset high width t rsth reset 2 t cyc ? stopc low width t stpl stopc 1 t rc ? reset fall time t rstf reset 20 ms 6 stopc rise time t stpr stopc 20 ms 7 input capacitance c in all pins except d 11 15 pf f = 1 mhz v in = 0 v, d 11 15 pf hd404628r, hd4046212r, hd404629r: f = 1 mhz, v in = 0 v 180 pf hd4074629: f = 1 mhz, v in = 0 v notes: 1. be sure to set system clock selection register (ssr) bits ssr1 and ssr0 to match the system clock oscillator frequency. 2. applies to voltage ranges v cc = 3.5 to 5.5 v for the hd4074629. 3. there are three oscillator stabilization times. (1) at power on, the time between the point where v cc reaches 2.7 v and the point where oscillation has stabilized. (2) at clearing stop mode, the time between the point where the reset pin reaches the high level and the point where oscillation has stabilized. (3) at clearing stop mode, the time between the point where the stopc pin reaches the low level and the point where oscillation has stabilized. at power on or when stop mode is cleared, reset or stopc must be input for at least t rc to ensure the oscillation stabilization time. since the oscillator stabilization time will depend on circuit constants and stray capacitances, determine the oscillator by consulting with the oscillator? manufacturer. be sure to set miscellaneous register (mis) bits mis1 and mis0 to match the system clock oscillator stabilization time. 4. refer to figure 108. 5. refer to figure 109. the t cyc unit applies when the mcu is in standby or active mode. the t subcyc unit applies when the mcu is in watch or subactive mode. 6. refer to figure 110. 7. refer to figure 111.
hd404629r series 149 serial interface timing characteristics (hd404628r, hd4046212r, hd404629r: v cc = 2.7 to 6.0 v, gnd = 0 v, t a = ?0 c to +75 c; hd4074629: v cc = 2.7 to 5.5 v, gnd = 0 v, t a = ?0 c to +75 c, unless otherwise specified) during transmit clock output item symbol pin min typ max unit test condition notes transmit clock cycle time t scyc sck 1.0 t cyc load shown in figure 113 1 transmit clock high width t sckh sck 0.5 t scyc load shown in figure 113 1 transmit clock low width t sckl sck 0.5 t scyc load shown in figure 113 1 transmit clock rise time t sckr sck 200 ns load shown in figure 113 1 transmit clock fall time t sckf sck 200 ns load shown in figure 113 1 serial output data delay time t dso so 500 ns load shown in figure 113 1 serial input data setup time t ssi si 300 ns 1 serial input data hold time t hsi si 300 ns 1 note: 1. refer to figure 112. during transmit clock input item symbol pin min typ max unit test condition notes transmit clock cycle time t scyc sck 1.0 t cyc ? transmit clock high width t sckh sck 0.5 t scyc ? transmit clock low width t sckl sck 0.5 t scyc ? transmit clock rise time t sckr sck 200 ns 1 transmit clock fall time t sckf sck 200 ns 1 serial output data delay time t dso so 500 ns load shown in figure 113 1 serial input data setup time t ssi si 300 ns 1 serial input data hold time t hsi si 300 ns 1 note: 1. refer to figure 112.
hd404629r series 150 gnd r = 100 k l tonec toner w r = 100 k l w figure 111 tone output load circuit gnd r = 100 k l tonec toner w figure 112 distortion and db cr load circuit t cpr t cpf v cc ?0.3 v 0.3 v osc 1 t cph t cpl 1/f cp figure 113 external clock timing 0.9v cc 0.1v cc int 0 to int 4 , evnb, evnd t ih t il figure 114 interrupt timing
hd404629r series 151 reset t rstf t rsth 0.9v cc 0.1v cc figure 115 reset timing t stpr t stpl 0.9v cc 0.1v cc stopc figure 116 stopc timing 0.9v cc 0.1v cc t dso t sckf t sckl t ssi t hsi t scyc t sckr 0.4 v v ?1.0 v cc v ?1.0 v (0.9v ) cc 0.4 v (0.1v ) sck so si note: v cc ?1.0 v and 0.4 v are the threshold voltages for transmit clock output, and 0.9v cc and 0.1v cc are the threshold voltages for transmit clock input. cc cc t sckh * * * figure 117 serial interface timing
hd404629r series 152 r l = 2.6 k w v cc 1s2074 h or equivalent r = 12 kw test point c = 30 pf figure 118 timing load circuit
hd404629r series 153 notes on rom out please pay attention to the following items regarding rom out. on rom out, fill the rom area indicated below with 1s to create the same data size as a 16-kword version (hd404629r). a 16-kword data size is required to change rom data to mask manufacturing data since the program used is for a 16-kword version. this limitation applies when using an eprom or a data base. vector address zero-page subroutine (64 words) pattern & program (8,192 words) not used vector address zero-page subroutine (64 words) pattern & program (12,288 words) not used rom 8-kword version: hd404628r address $2000?3fff rom 12-kword version: hd4046212r address $3000?3fff $0000 $000f $0010 $003f $0040 $1fff $2000 $3fff $0000 $000f $0010 $003f $0040 $2fff $3000 $3fff fill this area with 1s
hd404629r series 154 hd404628r/hd4046212r/ hd404629r option list please check off the appropriate applications and enter the necessary information. date of order / / customer department name rom code name lsi number (hitachi entry) 1. rom size hd404628r 8-kword hd4046212r 12-kword hd404629r 16-kword 2. optional functions * with 32-khz cpu operation, with time-base for clock * without 32-khz cpu operation, with time-base for clock without 32-khz cpu operation, without time-base for clock note: * options marked with an asterisk require a subsystem crystal oscillator (x1, x2). 3. rom code data type please specify the first type below (the upper bits and lower bits are mixed together), when using the eprom on-package microcomputer type (including ztat tm version). the upper bits and lower bits are mixed together. the upper five bits and lower five bits are programmed to the same eprom in alternating order (i.e., lululu...). the upper bits and lower bits are separated. the upper five bits and lower five bits are programmed to different eproms. 4. system oscillator (osc1 and osc2) ceramic oscillator f = mhz crystal oscillator f = mhz external clock f = mhz 5. stop mode used not used 6. package fp-100a fp-100b tfp-100b
hd404629r series 155 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail- safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products.

▲Up To Search▲

Price & Availability of HD4074629R

	To Download HD4074629R Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .